| Message ID | 20220307165519.38380-4-kyarlagadda@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Tegra QUAD SPI combined sequence mode | expand |
On 07/03/2022 16:55, Krishna Yarlagadda wrote: > From: Ashish Singhal <ashishsingha@nvidia.com> > > This adds the QSPI controllers on the Tegra234 SoC and populates the > SPI NOR flash device for the Jetson AGX Orin platform. > > Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com> > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> > --- > .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 12 ++++++++ > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 28 +++++++++++++++++++ > include/dt-bindings/clock/tegra234-clock.h | 8 ++++++ > include/dt-bindings/reset/tegra234-reset.h | 2 ++ > 4 files changed, 50 insertions(+) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi > index d95a542c0bca..798de9226ba5 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi > @@ -7,6 +7,18 @@ > compatible = "nvidia,p3701-0000", "nvidia,tegra234"; > > bus@0 { > + spi@3270000 { > + status = "okay"; > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <102000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + }; > + }; > + > mmc@3460000 { > status = "okay"; > bus-width = <8>; > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > index aaace605bdaa..bd82b324703f 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > @@ -666,6 +666,34 @@ > #pwm-cells = <2>; > }; > > + spi@3270000 { > + compatible = "nvidia,tegra234-qspi"; > + reg = <0x3270000 0x1000>; > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, > + <&bpmp TEGRA234_CLK_QSPI0_PM>; > + clock-names = "qspi", "qspi_out"; > + resets = <&bpmp TEGRA234_RESET_QSPI0>; > + reset-names = "qspi"; > + status = "disabled"; > + }; Please sort these according to address. The above should be before the pwm@3280000 > + > + spi@3300000 { > + compatible = "nvidia,tegra234-qspi"; > + reg = <0x3300000 0x1000>; > + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, > + <&bpmp TEGRA234_CLK_QSPI1_PM>; > + clock-names = "qspi", "qspi_out"; > + resets = <&bpmp TEGRA234_RESET_QSPI1>; > + reset-names = "qspi"; > + status = "disabled"; > + }; > + > mmc@3460000 { > compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; > reg = <0x03460000 0x20000>; > diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h > index 8cae969e8cba..bd4c3086a2da 100644 > --- a/include/dt-bindings/clock/tegra234-clock.h > +++ b/include/dt-bindings/clock/tegra234-clock.h > @@ -140,6 +140,14 @@ > #define TEGRA234_CLK_PEX2_C9_CORE 173U > /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ > #define TEGRA234_CLK_PEX2_C10_CORE 187U > +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ > +#define TEGRA234_CLK_QSPI0_2X_PM 192U > +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ > +#define TEGRA234_CLK_QSPI1_2X_PM 193U > +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ > +#define TEGRA234_CLK_QSPI0_PM 194U > +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ > +#define TEGRA234_CLK_QSPI1_PM 195U > /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ > #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U > /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ > diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h > index 1362cd5e03f0..1652d8d9e106 100644 > --- a/include/dt-bindings/reset/tegra234-reset.h > +++ b/include/dt-bindings/reset/tegra234-reset.h > @@ -41,6 +41,8 @@ > #define TEGRA234_RESET_PWM7 74U > #define TEGRA234_RESET_PWM8 75U > #define TEGRA234_RESET_SDMMC4 85U > +#define TEGRA234_RESET_QSPI0 76U > +#define TEGRA234_RESET_QSPI1 77U Please sort according to value > #define TEGRA234_RESET_UARTA 100U > #define TEGRA234_RESET_PEX0_CORE_0 116U > #define TEGRA234_RESET_PEX0_CORE_1 117U
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index d95a542c0bca..798de9226ba5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -7,6 +7,18 @@ compatible = "nvidia,p3701-0000", "nvidia,tegra234"; bus@0 { + spi@3270000 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <102000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + mmc@3460000 { status = "okay"; bus-width = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index aaace605bdaa..bd82b324703f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -666,6 +666,34 @@ #pwm-cells = <2>; }; + spi@3270000 { + compatible = "nvidia,tegra234-qspi"; + reg = <0x3270000 0x1000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI0_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA234_RESET_QSPI0>; + reset-names = "qspi"; + status = "disabled"; + }; + + spi@3300000 { + compatible = "nvidia,tegra234-qspi"; + reg = <0x3300000 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI1_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA234_RESET_QSPI1>; + reset-names = "qspi"; + status = "disabled"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8cae969e8cba..bd4c3086a2da 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -140,6 +140,14 @@ #define TEGRA234_CLK_PEX2_C9_CORE 173U /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ #define TEGRA234_CLK_PEX2_C10_CORE 187U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ +#define TEGRA234_CLK_QSPI0_2X_PM 192U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ +#define TEGRA234_CLK_QSPI1_2X_PM 193U +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ +#define TEGRA234_CLK_QSPI0_PM 194U +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ +#define TEGRA234_CLK_QSPI1_PM 195U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 1362cd5e03f0..1652d8d9e106 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -41,6 +41,8 @@ #define TEGRA234_RESET_PWM7 74U #define TEGRA234_RESET_PWM8 75U #define TEGRA234_RESET_SDMMC4 85U +#define TEGRA234_RESET_QSPI0 76U +#define TEGRA234_RESET_QSPI1 77U #define TEGRA234_RESET_UARTA 100U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U