| Message ID | 20220317162349.739636-12-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 335f57508a7a3220feb161400f0475e7f42be1b3 |
| Headers | show |
| Series | None | expand |
On 3/17/22 11:23 AM, Andre Przywara wrote: > The F1C100 series contains two SPI controllers, and many boards use SPI0 > for a SPI flash, as the BROM is able to boot from that. > > Describe the two controllers in the SoC .dtsi, and also add the PortC > pins for SPI0, since this is where BROM looks at when trying to boot > from the commonly used SPI flash. > > The SPI controller seems to be the same as in the H3 chips, but it lacks > a separate mod clock. The manual says it's connected to AHB directly. > We don't export that AHB clock directly, but can use the AHB *gate* clock > as a clock source, since the SPI driver is not supposed to change the AHB > frequency anyway. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Samuel Holland <samuel@sholland.org>
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 59e0bd952f50..0edc1724407b 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -69,6 +69,34 @@ otg_sram: sram-section@0 { }; }; + spi0: spi@1c05000 { + compatible = "allwinner,suniv-f1c100s-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,suniv-f1c100s-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,suniv-f1c100s-mmc", "allwinner,sun7i-a20-mmc"; @@ -138,6 +166,11 @@ mmc0_pins: mmc0-pins { drive-strength = <30>; }; + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + uart0_pe_pins: uart0-pe-pins { pins = "PE0", "PE1"; function = "uart0";
The F1C100 series contains two SPI controllers, and many boards use SPI0 for a SPI flash, as the BROM is able to boot from that. Describe the two controllers in the SoC .dtsi, and also add the PortC pins for SPI0, since this is where BROM looks at when trying to boot from the commonly used SPI flash. The SPI controller seems to be the same as in the H3 chips, but it lacks a separate mod clock. The manual says it's connected to AHB directly. We don't export that AHB clock directly, but can use the AHB *gate* clock as a clock source, since the SPI driver is not supposed to change the AHB frequency anyway. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)