| Message ID | 20220419084640.191299-2-matthias.schiffer@ew.tq-group.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 1aeda0966693574c07c5fa72adf41be43d491f96 |
| Headers | show |
| Series | [1/2] spi: cadence-quadspi: further simplify cqspi_set_protocol() | expand |
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 96d14f3847b5..08f39f52e32a 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1370,13 +1370,7 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, return false; if (op->data.nbytes && op->data.buswidth != 8) return false; - } else if (all_false) { - /* Only 1-1-X ops are supported without DTR */ - if (op->cmd.nbytes && op->cmd.buswidth > 1) - return false; - if (op->addr.nbytes && op->addr.buswidth > 1) - return false; - } else { + } else if (!all_false) { /* Mixed DTR modes are not supported. */ return false; }
With the improved cqspi_set_protocol(), ops with cmd/addr buswidth >1 are now working correctly. Tested on a TI AM64x with a Macronix MX25U51245G QSPI flash using 1-4-4 operations. DTR operations are currently untested, so we leave them disabled for now (except for the previosly allowed 8-8-8 ops). Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> --- drivers/spi/spi-cadence-quadspi.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-)