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Wed, 18 May 2022 23:46:05 +0000 Date: Thu, 19 May 2022 08:46:04 +0900 (JST) Message-Id: <20220519.084604.966119051165023533.atsushi.nemoto@sord.co.jp> To: linux-spi@vger.kernel.org Cc: Mark Brown , Vignesh Raghavendra Subject: [PATCH v2] spi: spi-ti-qspi: Support per-transfer and per-slave speed_hz settings From: Atsushi Nemoto X-Mailer: Mew version 6.8 on Emacs 27.1 X-ClientProxiedBy: TYCPR01CA0027.jpnprd01.prod.outlook.com (2603:1096:405:1::15) To OSZPR01MB7049.jpnprd01.prod.outlook.com (2603:1096:604:13c::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0fbca791-7646-40d6-1987-08da392892f5 X-MS-TrafficTypeDiagnostic: OS3PR01MB10342:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wl2P+S3rlW9dPze5XkG+tz3kPtwv2r3C8lU3lFX13Mr/lD7Uj7r1NHWfWhqEwJHx1g5YZw7sNnJnWeqnRkAgTrWv1+L+yXjRuAaQfR+tETBjEwuDd5jcHbKZZa54fV1MMFPeX+Kzwsyg7RXo/dhiqSz9DbHYrV+hqMU6altybnt5/tBdA+KWwA0hkT5WqPP8bvpZLJD/EUotLMCQdJm3GGcFVYXaS0/4U1JfXZKZjVrekQ486uC5BFY/eSJfiTECztfrrjiH8pTWKGunYSMvnYo8WHgNkvl83davy9Rw1Er80kVPM7q9Jo0cMRyRoXDeprkJV8Wm+BXhLYSHymPjH30VRvpEhdCyJ2sgIG2bvEv54AWGoSh2qaKCOObSgC6fRFHWJ3sTIELuNeGLOSKr0JkDrV7vkcIav3HpLm4r5b3ZYNT48QxFtpuJJ0D4PuCNROoFME4p7lGmJU1+lj9M/mkjUdbInwunx54yxmAL2MlYa1LaBZVfVgAW6G+uSVoQaKCWOndwri2FWwtm0dlZcvW092BxzMm03hjD+ZZWj3H8Jxr3OjHaaPJHfsEPcw9BSccsF2wnllV406OK45o59Rfr1JIovJ7PoiOMWqQgoOlKVg/MHkCF7tswAA4+5i1jbQXYN4gl/bLuEkRJ35FjuGRWJSdb465oa6ryuK+fE+YYAGImdisufeQxO8+76JM8QsiQ4gJYTq2KkRIIg0olmA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:OSZPR01MB7049.jpnprd01.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(366004)(66556008)(66476007)(66946007)(103116003)(6512007)(8936002)(5660300002)(6486002)(83380400001)(4326008)(44832011)(508600001)(8676002)(26005)(36756003)(6916009)(316002)(54906003)(38350700002)(38100700002)(52116002)(186003)(2906002)(6506007)(86362001)(2616005);DIR:OUT;SFP:1101; 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Isolate clock settings out from ti_qspi_setup() and call it from ti_qspi_start_transfer_one() and ti_qspi_exec_mem_op(), using per-transfer speed_hz and per-slave max_speed_hz settings. Also drop spi_max_frequency from struct ti_qspi and use spi_master's max_speed_hz. Signed-off-by: Atsushi Nemoto --- Changes from v1: - rebase against broonie/spi.git for-next branch - use pm_runtime_resume_and_get instead of pm_runtime_get_sync drivers/spi/spi-ti-qspi.c | 75 ++++++++++++++++++++------------------- 1 file changed, 39 insertions(+), 36 deletions(-) diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index b5b65d882d7a..60086869bcae 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -57,7 +57,6 @@ struct ti_qspi { void *rx_bb_addr; struct dma_chan *rx_chan; - u32 spi_max_frequency; u32 cmd; u32 dc; @@ -140,37 +139,19 @@ static inline void ti_qspi_write(struct ti_qspi *qspi, static int ti_qspi_setup(struct spi_device *spi) { struct ti_qspi *qspi = spi_master_get_devdata(spi->master); - struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; - int clk_div = 0, ret; - u32 clk_ctrl_reg, clk_rate, clk_mask; + int ret; if (spi->master->busy) { dev_dbg(qspi->dev, "master busy doing other transfers\n"); return -EBUSY; } - if (!qspi->spi_max_frequency) { + if (!qspi->master->max_speed_hz) { dev_err(qspi->dev, "spi max frequency not defined\n"); return -EINVAL; } - clk_rate = clk_get_rate(qspi->fclk); - - clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1; - - if (clk_div < 0) { - dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n"); - return -EINVAL; - } - - if (clk_div > QSPI_CLK_DIV_MAX) { - dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n", - QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1); - return -EINVAL; - } - - dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", - qspi->spi_max_frequency, clk_div); + spi->max_speed_hz = min(spi->max_speed_hz, qspi->master->max_speed_hz); ret = pm_runtime_resume_and_get(qspi->dev); if (ret < 0) { @@ -178,18 +159,6 @@ static int ti_qspi_setup(struct spi_device *spi) return ret; } - clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); - - clk_ctrl_reg &= ~QSPI_CLK_EN; - - /* disable SCLK */ - ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); - - /* enable SCLK */ - clk_mask = QSPI_CLK_EN | clk_div; - ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); - ctx_reg->clkctrl = clk_mask; - pm_runtime_mark_last_busy(qspi->dev); ret = pm_runtime_put_autosuspend(qspi->dev); if (ret < 0) { @@ -200,6 +169,37 @@ static int ti_qspi_setup(struct spi_device *spi) return 0; } +static void ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz) +{ + struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; + int clk_div; + u32 clk_ctrl_reg, clk_rate, clk_ctrl_new; + + clk_rate = clk_get_rate(qspi->fclk); + clk_div = DIV_ROUND_UP(clk_rate, speed_hz) - 1; + clk_div = clamp(clk_div, 0, QSPI_CLK_DIV_MAX); + dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", speed_hz, clk_div); + + pm_runtime_resume_and_get(qspi->dev); + + clk_ctrl_new = QSPI_CLK_EN | clk_div; + if (ctx_reg->clkctrl != clk_ctrl_new) { + clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); + + clk_ctrl_reg &= ~QSPI_CLK_EN; + + /* disable SCLK */ + ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); + + /* enable SCLK */ + ti_qspi_write(qspi, clk_ctrl_new, QSPI_SPI_CLOCK_CNTRL_REG); + ctx_reg->clkctrl = clk_ctrl_new; + } + + pm_runtime_mark_last_busy(qspi->dev); + pm_runtime_put_autosuspend(qspi->dev); +} + static void ti_qspi_restore_ctx(struct ti_qspi *qspi) { struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; @@ -623,8 +623,10 @@ static int ti_qspi_exec_mem_op(struct spi_mem *mem, mutex_lock(&qspi->list_lock); - if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select) + if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select) { + ti_qspi_setup_clk(qspi, mem->spi->max_speed_hz); ti_qspi_enable_memory_map(mem->spi); + } ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth, op->addr.nbytes, op->dummy.nbytes); @@ -701,6 +703,7 @@ static int ti_qspi_start_transfer_one(struct spi_master *master, wlen = t->bits_per_word >> 3; transfer_len_words = min(t->len / wlen, frame_len_words); + ti_qspi_setup_clk(qspi, t->speed_hz); ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen); if (ret) { dev_dbg(qspi->dev, "transfer message failed\n"); @@ -851,7 +854,7 @@ static int ti_qspi_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) - qspi->spi_max_frequency = max_freq; + master->max_speed_hz = max_freq; dma_cap_zero(mask); dma_cap_set(DMA_MEMCPY, mask);