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Tue, 7 Jun 2022 11:47:11 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 7 Jun 2022 04:47:10 -0700 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Tue, 7 Jun 2022 04:47:07 -0700 From: Krishna Yarlagadda To: , , , , , , CC: , , , , "Krishna Yarlagadda" Subject: [Patch V3 1/3] spi: tegra210-quad: Multi-cs support Date: Tue, 7 Jun 2022 17:16:57 +0530 Message-ID: <20220607114659.54314-2-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220607114659.54314-1-kyarlagadda@nvidia.com> References: <20220607114659.54314-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fbdb6315-2af2-44e1-7083-08da487b75f3 X-MS-TrafficTypeDiagnostic: MW3PR12MB4555:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2022 11:47:12.2162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fbdb6315-2af2-44e1-7083-08da487b75f3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4555 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Tegra Grace and later chips can support upto 4 chip select lines for QUAD SPI. Added new compatible for Tegra Grace. Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 66f647f32876..c89592b21ffc 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -37,6 +37,16 @@ #define QSPI_RX_EN BIT(12) #define QSPI_CS_SW_VAL BIT(20) #define QSPI_CS_SW_HW BIT(21) + +#define QSPI_CS_POL_INACTIVE(n) (1 << (22 + (n))) +#define QSPI_CS_POL_INACTIVE_MASK (0xF << 22) +#define QSPI_CS_SEL_0 (0 << 26) +#define QSPI_CS_SEL_1 (1 << 26) +#define QSPI_CS_SEL_2 (2 << 26) +#define QSPI_CS_SEL_3 (3 << 26) +#define QSPI_CS_SEL_MASK (3 << 26) +#define QSPI_CS_SEL(x) (((x) & 0x3) << 26) + #define QSPI_CONTROL_MODE_0 (0 << 28) #define QSPI_CONTROL_MODE_3 (3 << 28) #define QSPI_CONTROL_MODE_MASK (3 << 28) @@ -154,6 +164,7 @@ struct tegra_qspi_soc_data { bool has_dma; bool cmb_xfer_capable; + unsigned int cs_count; }; struct tegra_qspi_client_data { @@ -812,6 +823,7 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran tegra_qspi_mask_clear_irq(tqspi); command1 = tqspi->def_command1_reg; + command1 |= QSPI_CS_SEL(spi->chip_select); command1 |= QSPI_BIT_LENGTH(bits_per_word - 1); command1 &= ~QSPI_CONTROL_MODE_MASK; @@ -941,10 +953,11 @@ static int tegra_qspi_setup(struct spi_device *spi) /* keep default cs state to inactive */ val = tqspi->def_command1_reg; + val |= QSPI_CS_SEL(spi->chip_select); if (spi->mode & SPI_CS_HIGH) - val &= ~QSPI_CS_SW_VAL; + val &= ~QSPI_CS_POL_INACTIVE(spi->chip_select); else - val |= QSPI_CS_SW_VAL; + val |= QSPI_CS_POL_INACTIVE(spi->chip_select); tqspi->def_command1_reg = val; tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); @@ -1425,16 +1438,25 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data) static struct tegra_qspi_soc_data tegra210_qspi_soc_data = { .has_dma = true, .cmb_xfer_capable = false, + .cs_count = 1, }; static struct tegra_qspi_soc_data tegra186_qspi_soc_data = { .has_dma = true, .cmb_xfer_capable = true, + .cs_count = 1, }; static struct tegra_qspi_soc_data tegra234_qspi_soc_data = { .has_dma = false, .cmb_xfer_capable = true, + .cs_count = 1, +}; + +static struct tegra_qspi_soc_data tegra241_qspi_soc_data = { + .has_dma = false, + .cmb_xfer_capable = true, + .cs_count = 4, }; static const struct of_device_id tegra_qspi_of_match[] = { @@ -1450,6 +1472,9 @@ static const struct of_device_id tegra_qspi_of_match[] = { }, { .compatible = "nvidia,tegra234-qspi", .data = &tegra234_qspi_soc_data, + }, { + .compatible = "nvidia,tegra241-qspi", + .data = &tegra241_qspi_soc_data, }, {} }; @@ -1467,6 +1492,9 @@ static const struct acpi_device_id tegra_qspi_acpi_match[] = { }, { .id = "NVDA1413", .driver_data = (kernel_ulong_t)&tegra234_qspi_soc_data, + }, { + .id = "NVDA1513", + .driver_data = (kernel_ulong_t)&tegra241_qspi_soc_data, }, {} }; @@ -1506,6 +1534,7 @@ static int tegra_qspi_probe(struct platform_device *pdev) spin_lock_init(&tqspi->lock); tqspi->soc_data = device_get_match_data(&pdev->dev); + master->num_chipselect = tqspi->soc_data->cs_count; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); tqspi->base = devm_ioremap_resource(&pdev->dev, r); if (IS_ERR(tqspi->base))