| Message ID | 20221012152135.28353-1-mauro.lima@eclypsium.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 |
| Headers | show |
| Series | spi: intel: Fix the offset to get the 64K erase opcode | expand |
On Wed, Oct 12, 2022 at 12:21:35PM -0300, Mauro Lima wrote: > According to documentation, the 64K erase opcode is located in VSCC > range [16:23] instead of [8:15]. > Use the proper value to shift the mask over the correct range. > > Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
On Wed, 12 Oct 2022 12:21:35 -0300, Mauro Lima wrote: > According to documentation, the 64K erase opcode is located in VSCC > range [16:23] instead of [8:15]. > Use the proper value to shift the mask over the correct range. > > Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/1] spi: intel: Fix the offset to get the 64K erase opcode commit: 6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c index 55f4ee2db002..605acb1bf4b0 100644 --- a/drivers/spi/spi-intel.c +++ b/drivers/spi/spi-intel.c @@ -114,7 +114,7 @@ #define ERASE_OPCODE_SHIFT 8 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_SHIFT 16 -#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) +#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT) /* Flash descriptor fields */ #define FLVALSIG_MAGIC 0x0ff0a55a
According to documentation, the 64K erase opcode is located in VSCC range [16:23] instead of [8:15]. Use the proper value to shift the mask over the correct range. Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> --- drivers/spi/spi-intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)