| Message ID | 20221105185911.1547847-5-j.neuschaefer@gmx.net (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Nuvoton WPCM450 FIU SPI flash controller | expand |
On 05/11/2022 19:59, Jonathan Neuschäfer wrote: > The Shared Memory interface (SHM) is a piece of hardware in Nuvoton BMCs > that allows a host processor (connected via LPC) to access flash and RAM > that belong to the BMC. The SHM includes a register block accessible from > the BMC side. > > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Sat, 05 Nov 2022, Jonathan Neuschäfer wrote: > The Shared Memory interface (SHM) is a piece of hardware in Nuvoton BMCs > that allows a host processor (connected via LPC) to access flash and RAM > that belong to the BMC. The SHM includes a register block accessible from > the BMC side. > > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> > --- > Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + > 1 file changed, 1 insertion(+) Applied, thanks.
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 4e4baf53796de..1b01bd0104316 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -53,6 +53,7 @@ properties: - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep + - nuvoton,wpcm450-shm - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos
The Shared Memory interface (SHM) is a piece of hardware in Nuvoton BMCs that allows a host processor (connected via LPC) to access flash and RAM that belong to the BMC. The SHM includes a register block accessible from the BMC side. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.35.1