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[5/8] ARM: dts: wpcm450: Add FIU SPI controller node

Message ID 20221105185911.1547847-6-j.neuschaefer@gmx.net (mailing list archive)
State Superseded
Headers show
Series Nuvoton WPCM450 FIU SPI flash controller | expand

Commit Message

J. Neuschäfer Nov. 5, 2022, 6:59 p.m. UTC 
Add the SPI controller (FIU, Flash Interface Unit) to the WPCM450
devicetree, according to the newly defined binding, as well as the SHM
(shared memory interface) syscon.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
---

This patch depends on the series:

	[PATCH v5 0/6] Nuvoton WPCM450 clock and reset driver
---
 arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

--
2.35.1
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
index 439f9047ad651..299fcbba3089b 100644
--- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
+++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
@@ -470,5 +470,21 @@  hg7_pins: mux-hg7 {
 				function = "hg7";
 			};
 		};
+
+		fiu: spi-controller@c8000000 {
+			compatible = "nuvoton,wpcm450-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>;
+			reg-names = "control", "memory";
+			clocks = <&clk WPCM450_CLK_FIU>;
+			status = "disabled";
+		};
+
+		shm: syscon@c8001000 {
+			compatible = "nuvoton,wpcm450-shm", "syscon";
+			reg = <0xc8001000 0x1000>;
+			reg-io-width = <1>;
+		};
 	};
 };