From patchwork Mon Nov 28 02:06:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiangsheng Hou X-Patchwork-Id: 13056955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 133EEC43217 for ; Mon, 28 Nov 2022 02:08:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229805AbiK1CIF (ORCPT ); Sun, 27 Nov 2022 21:08:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbiK1CIB (ORCPT ); Sun, 27 Nov 2022 21:08:01 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34A065FCC; Sun, 27 Nov 2022 18:07:56 -0800 (PST) X-UUID: c69ff013172c47bea53e2ca8ffc97a88-20221128 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=P0lzjUqPkXtCw2u3E1g0XvfNQEmHlZGE4XKWJ8ANQgc=; b=Dt3g9x33pAKLE695tnCh0SHI33sJdp2cj2Ssf+GzvPZg/Ry8cgrPiyeX1FXEhs4GLo5/2ZwNWE2bIGkcaSRr5N/rkLUB8FeL3QxPRcsbnmj1H2DwqdzOVgw3cS4ASuY40mBzdFusREM1WiDKusoZTAK5BLt0A3gr9e5zjGIQm0g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:631b3d4b-37a0-4a26-bf66-4b6adb636da6,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.14,REQID:631b3d4b-37a0-4a26-bf66-4b6adb636da6,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:dcaaed0,CLOUDID:369f721e-5e1d-4ab5-ab8e-3e04efc02b30,B ulkID:221128100751MTJBYYM7,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: c69ff013172c47bea53e2ca8ffc97a88-20221128 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 285950718; Mon, 28 Nov 2022 10:07:51 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 28 Nov 2022 10:07:49 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 28 Nov 2022 10:07:49 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Mark Brown , Chuanhong Guo CC: Xiangsheng Hou , , , , , , , , Subject: [PATCH 5/9] dt-bindings: spi: mtk-snfi: add mt7986 IC snfi bindings Date: Mon, 28 Nov 2022 10:06:09 +0800 Message-ID: <20221128020613.14821-6-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> References: <20221128020613.14821-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org 1. add mt7986 IC bindings 2. add optional nfi_hclk property which needed for mt7986 Signed-off-by: Xiangsheng Hou --- .../devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml index 6e6e02c91780..ee20075cd0e7 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -26,6 +26,7 @@ properties: enum: - mediatek,mt7622-snand - mediatek,mt7629-snand + - mediatek,mt7986-snand reg: items: @@ -36,14 +37,19 @@ properties: - description: NFI interrupt clocks: + minItems: 2 items: - description: clock used for the controller - description: clock used for the SPI bus + - description: clock used for the AHB bus dma bus, this depends on + hardware design, so this is optional. clock-names: + minItems: 2 items: - const: nfi_clk - const: pad_clk + - const: nfi_hclk nand-ecc-engine: description: device-tree node of the accompanying ECC engine.