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[78.150.37.98]) by smtp.gmail.com with ESMTPSA id t123-20020a1c4681000000b003a3170a7af9sm10156808wma.4.2022.12.12.10.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 10:07:41 -0800 (PST) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: jude.onyenegecha@sifive.com, ben.dooks@sifive.com, jeegar.lakhani@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sudip Mukherjee Subject: [PATCH v2 01/15] spi: dw: Introduce spi_frf and STD_SPI Date: Mon, 12 Dec 2022 18:07:18 +0000 Message-Id: <20221212180732.79167-2-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221212180732.79167-1-sudip.mukherjee@sifive.com> References: <20221212180732.79167-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The DW APB SSI controllers of v4.x and newer and DW AHB SSI controllers supports enhanced SPI modes which can be defined from SPI_FRF of DW_SPI_CTRLR0 register. Without enhanced mode, these controllers will work in the standard spi mode. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 13 ++++++++++++- drivers/spi/spi-dw.h | 6 ++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 99edddf9958b9..77c23772bb3d9 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -333,6 +333,16 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, /* CTRLR0[11:10] Transfer Mode */ cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode); + if (dw_spi_ver_is_ge(dws, HSSI, 103A)) { + cr0 &= ~DW_HSSI_CTRLR0_SPI_FRF_MASK; + cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_SPI_FRF_MASK, + cfg->spi_frf); + } else if (dw_spi_ver_is_ge(dws, PSSI, 400A)) { + cr0 &= ~DW_PSSI_CTRLR0_SPI_FRF_MASK; + cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_SPI_FRF_MASK, + cfg->spi_frf); + } + dw_writel(dws, DW_SPI_CTRLR0, cr0); if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD || @@ -422,6 +432,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, .tmode = DW_SPI_CTRLR0_TMOD_TR, .dfs = transfer->bits_per_word, .freq = transfer->speed_hz, + .spi_frf = DW_SPI_CTRLR0_SPI_FRF_STD_SPI, }; int ret; @@ -664,7 +675,7 @@ static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi) static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller); - struct dw_spi_cfg cfg; + struct dw_spi_cfg cfg = {0}; unsigned long flags; int ret; diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 9e8eb2b52d5c7..414a415deb42a 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -17,6 +17,8 @@ /* Synopsys DW SSI component versions (FourCC sequence) */ #define DW_HSSI_102A 0x3130322a +#define DW_HSSI_103A 0x3130332a +#define DW_PSSI_400A 0x3430302a /* DW SSI IP-core ID and version check helpers */ #define dw_spi_ip_is(_dws, _ip) \ @@ -94,6 +96,9 @@ #define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10) #define DW_HSSI_CTRLR0_SRL BIT(13) #define DW_HSSI_CTRLR0_MST BIT(31) +#define DW_HSSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22) +#define DW_PSSI_CTRLR0_SPI_FRF_MASK GENMASK(22, 21) +#define DW_SPI_CTRLR0_SPI_FRF_STD_SPI 0x0 /* Bit fields in CTRLR1 */ #define DW_SPI_NDF_MASK GENMASK(15, 0) @@ -135,6 +140,7 @@ struct dw_spi_cfg { u8 dfs; u32 ndf; u32 freq; + u8 spi_frf; }; struct dw_spi;