[2/2] spi: spi-fsl-qspi: support setting sampling delay through devicetree

Commit Message

Mario Kicherer Jan. 16, 2023, 11:50 a.m. UTC

The internal sampling point of incoming data can be delayed by modifying
the QuadSPI_SMPR register. This patch enables setting this delay using a
device tree entry.

Signed-off-by: Mario Kicherer <[e-mail]>
---
 drivers/spi/spi-fsl-qspi.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

Patch

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index 85cc71ba624a..10faaf57db28 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -722,6 +722,7 @@  static int fsl_qspi_default_setup(struct fsl_qspi *q)
 {
 	void __iomem *base = q->iobase;
 	u32 reg, addr_offset = 0;
+	u8 sampling_delay;
 	int ret;
 
 	/* disable and unprepare clock to avoid glitch pass to controller */
@@ -756,10 +757,22 @@  static int fsl_qspi_default_setup(struct fsl_qspi *q)
 			    base + QUADSPI_FLSHCR);
 
 	reg = qspi_readl(q, base + QUADSPI_SMPR);
-	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
-			| QUADSPI_SMPR_FSPHS_MASK
-			| QUADSPI_SMPR_HSENA_MASK
-			| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
+	reg = reg & ~(QUADSPI_SMPR_FSDLY_MASK
+		      | QUADSPI_SMPR_FSPHS_MASK
+		      | QUADSPI_SMPR_HSENA_MASK
+		      | QUADSPI_SMPR_DDRSMP_MASK);
+	ret = of_property_read_u8(q->dev->of_node,
+				   "fsl,qspi-sampling-delay",
+				   &sampling_delay);
+	if (!ret) {
+		if (sampling_delay <= 3)
+			reg = reg | (sampling_delay << 5);
+		else
+			dev_err(q->dev,
+				"fsl,qspi-sampling_delay %u greater than 3\n",
+				sampling_delay);
+	}
+	qspi_writel(q, reg, base + QUADSPI_SMPR);
 
 	/* We only use the buffer3 for AHB read */
 	qspi_writel(q, 0, base + QUADSPI_BUF0IND);