[27/35] Documentation: spi: correct spelling

Commit Message

Randy Dunlap Jan. 27, 2023, 6:39 a.m. UTC

Correct spelling problems for Documentation/spi/ as reported
by codespell.

Signed-off-by: Randy Dunlap <[e-mail]>
Cc: Mark Brown <[e-mail]>
Cc: [e-mail]
Cc: Jonathan Corbet <[e-mail]>
Cc: [e-mail]
---
 Documentation/spi/pxa2xx.rst      |   12 ++++++------
 Documentation/spi/spi-lm70llp.rst |    2 +-
 Documentation/spi/spi-summary.rst |    2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

Patch

diff -- a/Documentation/spi/pxa2xx.rst b/Documentation/spi/pxa2xx.rst
--- a/Documentation/spi/pxa2xx.rst
+++ b/Documentation/spi/pxa2xx.rst
@@ -141,15 +141,15 @@  field. Below is a sample configuration u
 ::
 
   static struct pxa2xx_spi_chip cs8415a_chip_info = {
-	.tx_threshold = 8, /* SSP hardward FIFO threshold */
-	.rx_threshold = 8, /* SSP hardward FIFO threshold */
+	.tx_threshold = 8, /* SSP hardware FIFO threshold */
+	.rx_threshold = 8, /* SSP hardware FIFO threshold */
 	.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
 	.timeout = 235, /* See Intel documentation */
   };
 
   static struct pxa2xx_spi_chip cs8405a_chip_info = {
-	.tx_threshold = 8, /* SSP hardward FIFO threshold */
-	.rx_threshold = 8, /* SSP hardward FIFO threshold */
+	.tx_threshold = 8, /* SSP hardware FIFO threshold */
+	.rx_threshold = 8, /* SSP hardware FIFO threshold */
 	.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
 	.timeout = 235, /* See Intel documentation */
   };
@@ -157,7 +157,7 @@  field. Below is a sample configuration u
   static struct spi_board_info streetracer_spi_board_info[] __initdata = {
 	{
 		.modalias = "cs8415a", /* Name of spi_driver for this device */
-		.max_speed_hz = 3686400, /* Run SSP as fast a possbile */
+		.max_speed_hz = 3686400, /* Run SSP as fast a possible */
 		.bus_num = 2, /* Framework bus number */
 		.chip_select = 0, /* Framework chip select */
 		.platform_data = NULL; /* No spi_driver specific config */
@@ -166,7 +166,7 @@  field. Below is a sample configuration u
 	},
 	{
 		.modalias = "cs8405a", /* Name of spi_driver for this device */
-		.max_speed_hz = 3686400, /* Run SSP as fast a possbile */
+		.max_speed_hz = 3686400, /* Run SSP as fast a possible */
 		.bus_num = 2, /* Framework bus number */
 		.chip_select = 1, /* Framework chip select */
 		.controller_data = &cs8405a_chip_info, /* Master chip config */
diff -- a/Documentation/spi/spi-lm70llp.rst b/Documentation/spi/spi-lm70llp.rst
--- a/Documentation/spi/spi-lm70llp.rst
+++ b/Documentation/spi/spi-lm70llp.rst
@@ -57,7 +57,7 @@  devices might share the same SI/SO pin.
 The bitbanger routine in this driver (lm70_txrx) is called back from
 the bound "hwmon/lm70" protocol driver through its sysfs hook, using a
 spi_write_then_read() call.  It performs Mode 0 (SPI/Microwire) bitbanging.
-The lm70 driver then inteprets the resulting digital temperature value
+The lm70 driver then interprets the resulting digital temperature value
 and exports it through sysfs.
 
 A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic
diff -- a/Documentation/spi/spi-summary.rst b/Documentation/spi/spi-summary.rst
--- a/Documentation/spi/spi-summary.rst
+++ b/Documentation/spi/spi-summary.rst
@@ -105,7 +105,7 @@  find isn't necessarily helpful.  The fou
  - CPHA indicates the clock phase used to sample data; CPHA=0 says
    sample on the leading edge, CPHA=1 means the trailing edge.
 
-   Since the signal needs to stablize before it's sampled, CPHA=0
+   Since the signal needs to stabilize before it's sampled, CPHA=0
    implies that its data is written half a clock before the first
    clock edge.  The chipselect may have made it become available.