From patchwork Thu Apr 27 12:33:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joy Chakraborty X-Patchwork-Id: 13225450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CF58C77B61 for ; Thu, 27 Apr 2023 12:33:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243721AbjD0Mdu (ORCPT ); Thu, 27 Apr 2023 08:33:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243848AbjD0Mdq (ORCPT ); Thu, 27 Apr 2023 08:33:46 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B4435BAE for ; Thu, 27 Apr 2023 05:33:40 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9968fb4a8cso9673318276.0 for ; Thu, 27 Apr 2023 05:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682598819; x=1685190819; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=fLvnCO6evlKbK+xj/d2Id6gaw49UQ3nh6G31gbqAkCk=; b=3DLTZ423zj75HZE3dLX2ol2fkvJhx+OfxNx9TMkA1hLwBabuiMsxVL4wEmuUfF45UQ +i0GLG+Em2uXwmyHcJLuJRz+vWS5vYw+EdRJvVSn8prLzEyev1YSa/j+nCoeGTno7mIi 56DwSlzeCplHTll72n8yKAasRvyfeO6rsIFX5krBUDP7yXf9nWgwyHjFnGAR7KN3XITs ggptjW7770nyYfIoSP2/MyjD9plolbqIVxbccmGTDnK3ijXt0EvYQzVSbjIXOrCmvRyb SThdIXn6S3njt7z3q77aTsYuoeW9Bbf8L+UTaIWZAOdV+J1f4sLYODoPz9ZCNsw1QcgN 7UJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682598819; x=1685190819; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=fLvnCO6evlKbK+xj/d2Id6gaw49UQ3nh6G31gbqAkCk=; b=hYZd0KzFkw30fvKK18QcDWXGHT7qo8or1KyZC+eOUHpLAaiKd+BfXrXtWxv8XQdZGN g3KGZi1XgCUzhPoUrn1ys9FU4dc21NUchMdsXWd8mHmxKMT8JQKeDCz0sL1XZMCn+95J Ztd+oypfay9xq6v5cL/kcjY5K78+3k+ZJ/zEhCU4f1WUwWe4QqEvk7qPfKgus1809UgK sKnmjWDDgDijWnEHqqXeoSDjZyQWN0MMvvINYX20aYRlJOohcjeLGWIy6XrzMXEBTx/S GPI8luc/KEE+x10SSONxRPI8u2FeZEOPSRVavp7YnlwZLoVsb78F7MWJXysuiOdsIE4F fBDA== X-Gm-Message-State: AC+VfDwddcd7P4xARDt+l4yxIGg9VIoTmk2TgM8AKkR4iFVm9BKLK+5R 0jISP0lsBSlBfdmjy9f+K9OCPzBIm4FPFQ== X-Google-Smtp-Source: ACHHUZ5LevSsh6HRBrQnVClBVBi411VD4CTn+FuRBCwVXmH1Jd1eK9ZdJzQVk/QPxH/fkPxKFPxWpQzlebhKeA== X-Received: from joychakr.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:6ea]) (user=joychakr job=sendgmr) by 2002:a25:5843:0:b0:b99:df0b:cb1e with SMTP id m64-20020a255843000000b00b99df0bcb1emr501204ybb.4.1682598819554; Thu, 27 Apr 2023 05:33:39 -0700 (PDT) Date: Thu, 27 Apr 2023 12:33:13 +0000 In-Reply-To: <20230427123314.1997152-1-joychakr@google.com> Mime-Version: 1.0 References: <20230427123314.1997152-1-joychakr@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Message-ID: <20230427123314.1997152-5-joychakr@google.com> Subject: [PATCH v9 4/5] spi: dw: Add DMA address widths capability check From: Joy Chakraborty To: Serge Semin , Mark Brown , Andy Shevchenko Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, manugautam@google.com, rohitner@google.com, Joy Chakraborty Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Store address width capabilities of DMA controller during init and check the same per transfer to make sure the bits/word requirement can be met. Current DW DMA driver requires both tx and rx channel to be configured and functional hence a subset of both tx and rx channel address width capability is checked with the width requirement(n_bytes) for a transfer. Signed-off-by: Joy Chakraborty Reviewed-by: Serge Semin Tested-by: Serge Semin * tested on Baikal-T1 based system with DW SPI-looped back interface transferring a chunk of data with DFS:8,12,16. --- drivers/spi/spi-dw-dma.c | 17 ++++++++++++++++- drivers/spi/spi-dw.h | 1 + 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c index 22d0727a3789..df819652901a 100644 --- a/drivers/spi/spi-dw-dma.c +++ b/drivers/spi/spi-dw-dma.c @@ -97,6 +97,15 @@ static int dw_spi_dma_caps_init(struct dw_spi *dws) dws->dma_sg_burst = rx.max_sg_burst; else dws->dma_sg_burst = 0; + + /* + * Assuming both channels belong to the same DMA controller hence the + * peripheral side address width capabilities most likely would be + * the same. + */ + dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths; + + return 0; } static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws) @@ -237,8 +246,14 @@ static bool dw_spi_can_dma(struct spi_controller *master, struct spi_device *spi, struct spi_transfer *xfer) { struct dw_spi *dws = spi_controller_get_devdata(master); + enum dma_slave_buswidth dma_bus_width; + + if (xfer->len <= dws->fifo_len) + return false; + + dma_bus_width = dw_spi_dma_convert_width(dws->n_bytes); - return xfer->len > dws->fifo_len; + return dws->dma_addr_widths & BIT(dma_bus_width); } static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 9e8eb2b52d5c..3962e6dcf880 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -190,6 +190,7 @@ struct dw_spi { struct dma_chan *rxchan; u32 rxburst; u32 dma_sg_burst; + u32 dma_addr_widths; unsigned long dma_chan_busy; dma_addr_t dma_addr; /* phy address of the Data register */ const struct dw_spi_dma_ops *dma_ops;