From patchwork Tue May 9 08:22:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joy Chakraborty X-Patchwork-Id: 13235477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E2B9C77B7C for ; Tue, 9 May 2023 08:23:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233637AbjEIIXZ (ORCPT ); Tue, 9 May 2023 04:23:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229615AbjEIIXP (ORCPT ); Tue, 9 May 2023 04:23:15 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4665F6187 for ; Tue, 9 May 2023 01:23:09 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-ba2b9ecfadaso4133358276.2 for ; Tue, 09 May 2023 01:23:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683620589; x=1686212589; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=HEl/ebklkKS4o01vG1eIpzniBnuA2urT/Tj2wNhU8Co=; b=qMMaRgFkwtCu3WTiH6Xcj3y05BVLosur4TdWR4cdbWaK8Yeo6AzJvfnwVOZObtkgIh lvB5saSwuLoXmapUFLdMuCrCRSeqgr/kvsHm8khWp10DIMzb3Ssgeo6mr7SZDTY5hsf3 5f5OO0unt09oLnbBKqb+wF/4DjCbAiXIA46f0Nh51pbQflCT4aQ4EZo0y8zlUON8cM/x LLv3WxLJLOR4IR+qUGenK5KcM5RFfU+uKpedI5QIy6TdrtW+7xfhDl+dfamVCOR2IX0l V9vdXIAl0kq63Qpse1lBDC8oEI4+8ykXxve/MYcd+LXtmhCLUFe3iocFXISnhKRi17cJ zQbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683620589; x=1686212589; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=HEl/ebklkKS4o01vG1eIpzniBnuA2urT/Tj2wNhU8Co=; b=cB5xXCqEzwfe53IB9ZxleDYRvJ6ps4iwcOYFiHdSnIBi62bzTq5nt9kOJjyNGQ7Q3V yBCoKXTljXUkTmpR+OWKTeWEXPvUM8rO4PVtd1OGXrES6ZgQGixEhe3mMJIQ1k/X/VdM y1oNgETE4gwadRVGa/zD8msI/i80hCZ8rcjY1LxabTzLVErbmJHNNn+x4/qVThTtImUW GVj5QLqWHJ7epqUDIFYyKSRq51flgIilQnoQ7Il+4+7Lk2BpLkV8YcutL5HxB/kNMq/Z BadOzBDSjgIGaTIrqoagPrLA79LsQqU3sQ7u5cDTQKPO9BoC2J+5HslRcdh9D0VUSWEU 74Kw== X-Gm-Message-State: AC+VfDzW5a7r/ELvyOhPq4xUBVIzXS66th8wqsNGQfYhn1kkYW9jty0g 9QdKt2NVb19UKfGpdV7qhwa5+yvC7kOpxg== X-Google-Smtp-Source: ACHHUZ4ut1ENLFwSZagCJcakA6qC3fueDQ6170UYRgz+XEsG3gRG9OhLosz9MmFGoRouyQ0KRlMwj8BufM8jew== X-Received: from joychakr.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:6ea]) (user=joychakr job=sendgmr) by 2002:a25:12d5:0:b0:ba1:af7b:b88d with SMTP id 204-20020a2512d5000000b00ba1af7bb88dmr8574837ybs.2.1683620589048; Tue, 09 May 2023 01:23:09 -0700 (PDT) Date: Tue, 9 May 2023 08:22:43 +0000 In-Reply-To: <20230509082244.1069623-1-joychakr@google.com> Mime-Version: 1.0 References: <20230509082244.1069623-1-joychakr@google.com> X-Mailer: git-send-email 2.40.1.521.gf1e218fcd8-goog Message-ID: <20230509082244.1069623-5-joychakr@google.com> Subject: [PATCH v10 4/5] spi: dw: Add DMA address widths capability check From: Joy Chakraborty To: Serge Semin , Mark Brown , Andy Shevchenko Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, manugautam@google.com, rohitner@google.com, Joy Chakraborty Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Store address width capabilities of DMA controller during init and check the same per transfer to make sure the bits/word requirement can be met. Current DW DMA driver requires both tx and rx channel to be configured and functional hence a subset of both tx and rx channel address width capability is checked with the width requirement(n_bytes) for a transfer. Signed-off-by: Joy Chakraborty Reviewed-by: Serge Semin Tested-by: Serge Semin * tested on Baikal-T1 based system with DW SPI-looped back interface transferring a chunk of data with DFS:8,12,16. --- drivers/spi/spi-dw-dma.c | 15 ++++++++++++++- drivers/spi/spi-dw.h | 1 + 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c index 2363317a0dca..df819652901a 100644 --- a/drivers/spi/spi-dw-dma.c +++ b/drivers/spi/spi-dw-dma.c @@ -98,6 +98,13 @@ static int dw_spi_dma_caps_init(struct dw_spi *dws) else dws->dma_sg_burst = 0; + /* + * Assuming both channels belong to the same DMA controller hence the + * peripheral side address width capabilities most likely would be + * the same. + */ + dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths; + return 0; } @@ -239,8 +246,14 @@ static bool dw_spi_can_dma(struct spi_controller *master, struct spi_device *spi, struct spi_transfer *xfer) { struct dw_spi *dws = spi_controller_get_devdata(master); + enum dma_slave_buswidth dma_bus_width; + + if (xfer->len <= dws->fifo_len) + return false; + + dma_bus_width = dw_spi_dma_convert_width(dws->n_bytes); - return xfer->len > dws->fifo_len; + return dws->dma_addr_widths & BIT(dma_bus_width); } static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 9e8eb2b52d5c..3962e6dcf880 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -190,6 +190,7 @@ struct dw_spi { struct dma_chan *rxchan; u32 rxburst; u32 dma_sg_burst; + u32 dma_addr_widths; unsigned long dma_chan_busy; dma_addr_t dma_addr; /* phy address of the Data register */ const struct dw_spi_dma_ops *dma_ops;