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[2003:c7:8700:c900:d536:eaeb:3276:9819]) by smtp.gmail.com with ESMTPSA id bu2-20020a170906a14200b0096654fdbe34sm12235758ejb.142.2023.05.17.03.30.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 03:30:46 -0700 (PDT) From: Boerge Struempfel Cc: boerge.struempfel@gmail.com, bstruempfel@ultratronik.de, andy.shevchenko@gmail.com, festevam@gmail.com, amit.kumar-mahapatra@amd.com, broonie@kernel.org, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] spi: spi-imx: add support for SPI_MOSI_IDLE_LOW mode bit Date: Wed, 17 May 2023 12:30:06 +0200 Message-Id: <20230517103007.26287-2-boerge.struempfel@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230517103007.26287-1-boerge.struempfel@gmail.com> References: <20230517103007.26287-1-boerge.struempfel@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org By default, the spi-imx controller pulls the mosi line high, whenever it is idle. This behaviour can be inverted per CS by setting the corresponding DATA_CTL bit in the config register of the controller. Also, since the controller mode-bits have to be touched anyways, the SPI_CPOL and SPI_CPHA are replaced by the combined SPI_MODE_X_MASK flag. Signed-off-by: Boerge Struempfel --- drivers/spi/spi-imx.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 34e5f81ec431..e5e55d66fecc 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -281,6 +281,7 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4)) #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8)) #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12)) +#define MX51_ECSPI_CONFIG_DATACTL(cs) (1 << ((cs & 3) + 16)) #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20)) #define MX51_ECSPI_INT 0x10 @@ -573,6 +574,11 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi_get_chipselect(spi, 0)); } + if (spi->mode & SPI_MOSI_IDLE_LOW) + cfg |= MX51_ECSPI_CONFIG_DATACTL(spi_get_chipselect(spi, 0)); + else + cfg &= ~MX51_ECSPI_CONFIG_DATACTL(spi_get_chipselect(spi, 0); + if (spi->mode & SPI_CS_HIGH) cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi_get_chipselect(spi, 0)); else @@ -1743,7 +1749,8 @@ static int spi_imx_probe(struct platform_device *pdev) spi_imx->controller->prepare_message = spi_imx_prepare_message; spi_imx->controller->unprepare_message = spi_imx_unprepare_message; spi_imx->controller->slave_abort = spi_imx_slave_abort; - spi_imx->controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; + spi_imx->controller->mode_bits = SPI_MODE_X_MASK | SPI_CS_HIGH | SPI_NO_CS | + SPI_MOSI_IDLE_LOW; if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx))