@@ -3,6 +3,7 @@ menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/actions/Kconfig"
source "drivers/soc/amlogic/Kconfig"
+source "drivers/soc/amd/Kconfig"
source "drivers/soc/apple/Kconfig"
source "drivers/soc/aspeed/Kconfig"
source "drivers/soc/atmel/Kconfig"
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_ARCH_ACTIONS) += actions/
+obj-$(CONFIG_ARCH_PENSANDO) += amd/
obj-y += apple/
obj-y += aspeed/
obj-$(CONFIG_ARCH_AT91) += atmel/
new file mode 100644
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "AMD Pensando SoC drivers"
+
+config AMD_PENSANDO_CTRL
+ tristate "AMD Pensando SoC Controller"
+ depends on SPI_MASTER=y
+ depends on (ARCH_PENSANDO && OF) || COMPILE_TEST
+ default ARCH_PENSANDO
+ select REGMAP_SPI
+ select MFD_SYSCON
+ help
+ Enables AMD Pensando SoC controller device support. This is a SPI
+ attached companion device in all Pensando SoC board designs which
+ provides essential board control/status registers and management IO
+ support.
+endmenu
new file mode 100644
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_AMD_PENSANDO_CTRL) += pensando-ctrl.o
new file mode 100644
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * AMD Pensando SoC Controller
+ *
+ * Userspace interface and reset driver support for SPI connected Pensando SoC
+ * controller device. This device is present in all Pensando SoC designs and
+ * contains board control/status registers and management IO support.
+ *
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/miscdevice.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/reset-controller.h>
+#include <linux/spi/spi.h>
+#include <linux/uaccess.h>
+
+#include <linux/amd-pensando-ctrl.h>
+
+struct penctrl_device {
+ struct reset_controller_dev rcdev;
+ struct spi_device *spi;
+};
+
+static struct penctrl_device *penctrl;
+static DEFINE_MUTEX(spi_lock);
+
+static long
+penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ struct penctrl_device *penctrl;
+ u8 tx_buf[PENCTRL_MAX_MSG_LEN];
+ u8 rx_buf[PENCTRL_MAX_MSG_LEN];
+ struct spi_transfer t[2] = {};
+ struct penctrl_spi_xfer *msg;
+ struct spi_device *spi;
+ unsigned int num_msgs;
+ struct spi_message m;
+ u32 size;
+ int ret;
+
+ /* Get a reference to the SPI device */
+ penctrl = filp->private_data;
+ if (!penctrl)
+ return -ESHUTDOWN;
+
+ spi = spi_dev_get(penctrl->spi);
+ if (!spi)
+ return -ESHUTDOWN;
+
+ /* Verify and prepare SPI message */
+ size = _IOC_SIZE(cmd);
+ num_msgs = size / sizeof(struct penctrl_spi_xfer);
+ if (num_msgs > 2 || size == 0 || size % sizeof(struct penctrl_spi_xfer)) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+ msg = memdup_user((struct penctrl_spi_xfer *)arg, size);
+ if (IS_ERR(msg)) {
+ ret = PTR_ERR(msg);
+ goto out_unlock;
+ }
+ if (msg->len > PENCTRL_MAX_MSG_LEN) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+
+ t[0].tx_buf = tx_buf;
+ t[0].len = msg->len;
+ if (copy_from_user(tx_buf, (void __user *)msg->tx_buf, msg->len)) {
+ ret = -EFAULT;
+ goto out_unlock;
+ }
+ if (num_msgs > 1) {
+ msg++;
+ if (msg->len > PENCTRL_MAX_MSG_LEN) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+ t[1].rx_buf = rx_buf;
+ t[1].len = msg->len;
+ }
+ spi_message_init_with_transfers(&m, t, num_msgs);
+
+ /* Perform the transfer */
+ mutex_lock(&spi_lock);
+ ret = spi_sync(spi, &m);
+ mutex_unlock(&spi_lock);
+
+ if (ret || (num_msgs == 1))
+ goto out_unlock;
+
+ if (copy_to_user((void __user *)msg->rx_buf, rx_buf, msg->len))
+ ret = -EFAULT;
+
+out_unlock:
+ spi_dev_put(spi);
+ return ret;
+}
+
+static int penctrl_open(struct inode *inode, struct file *filp)
+{
+ struct spi_device *spi;
+ u8 current_cs;
+
+ filp->private_data = penctrl;
+ current_cs = iminor(inode);
+ spi = penctrl->spi;
+ spi->chip_select = current_cs;
+ spi_set_csgpiod(spi, 0, spi->controller->cs_gpiods[current_cs]);
+ spi_setup(spi);
+ return stream_open(inode, filp);
+}
+
+static int penctrl_release(struct inode *inode, struct file *filp)
+{
+ filp->private_data = NULL;
+ return 0;
+}
+
+static const struct file_operations penctrl_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = penctrl_ioctl,
+ .open = penctrl_open,
+ .release = penctrl_release,
+ .llseek = no_llseek,
+};
+
+static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 *val)
+{
+ struct spi_device *spi = penctrl->spi;
+ struct spi_transfer t[2] = {};
+ struct spi_message m;
+ u8 txbuf[3];
+ u8 rxbuf[1];
+ int ret;
+
+ txbuf[0] = PENCTRL_SPI_CMD_REGRD;
+ txbuf[1] = reg;
+ txbuf[2] = 0;
+ t[0].tx_buf = txbuf;
+ t[0].len = sizeof(txbuf);
+
+ rxbuf[0] = 0;
+ t[1].rx_buf = rxbuf;
+ t[1].len = sizeof(rxbuf);
+
+ spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
+ ret = spi_sync(spi, &m);
+ if (ret)
+ return ret;
+
+ *val = rxbuf[0];
+ return 0;
+}
+
+static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32 val)
+{
+ struct spi_device *spi = penctrl->spi;
+ struct spi_transfer t = {};
+ struct spi_message m;
+ u8 txbuf[4];
+
+ txbuf[0] = PENCTRL_SPI_CMD_REGWR;
+ txbuf[1] = reg;
+ txbuf[2] = val;
+ txbuf[3] = 0;
+
+ t.tx_buf = txbuf;
+ t.len = sizeof(txbuf);
+ spi_message_init_with_transfers(&m, &t, 1);
+ return spi_sync(spi, &m);
+}
+
+static int penctrl_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct penctrl_device *penctrl =
+ container_of(rcdev, struct penctrl_device, rcdev);
+ struct spi_device *spi = penctrl->spi;
+ unsigned int val;
+ int ret;
+
+ mutex_lock(&spi_lock);
+ spi->chip_select = 0;
+ spi_set_csgpiod(spi, 0, spi->controller->cs_gpiods[0]);
+ spi_setup(spi);
+ ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
+ if (ret) {
+ dev_err(&spi->dev, "error reading ctrl0 reg\n");
+ goto out_unlock;
+ }
+
+ val |= BIT(6);
+ ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
+ if (ret)
+ dev_err(&spi->dev, "error writing ctrl0 reg\n");
+
+out_unlock:
+ mutex_unlock(&spi_lock);
+ return ret;
+}
+
+static int penctrl_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct penctrl_device *penctrl =
+ container_of(rcdev, struct penctrl_device, rcdev);
+ struct spi_device *spi = penctrl->spi;
+ unsigned int val;
+ int ret;
+
+ mutex_lock(&spi_lock);
+ spi->chip_select = 0;
+ spi_set_csgpiod(spi, 0, spi->controller->cs_gpiods[0]);
+ spi_setup(spi);
+ ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
+ if (ret) {
+ dev_err(&spi->dev, "error reading ctrl0 reg\n");
+ goto out_unlock;
+ }
+
+ val &= ~BIT(6);
+ ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
+ if (ret)
+ dev_err(&spi->dev, "error writing ctrl0 reg\n");
+
+out_unlock:
+ mutex_unlock(&spi_lock);
+ return ret;
+}
+
+static const struct reset_control_ops penctrl_reset_ops = {
+ .assert = penctrl_reset_assert,
+ .deassert = penctrl_reset_deassert,
+};
+
+static struct miscdevice penctrl_devices[] = {
+ { .minor = 0, .name = "penctrl.0", .fops = &penctrl_fops },
+ { .minor = 1, .name = "penctrl.1", .fops = &penctrl_fops },
+ { .minor = 2, .name = "penctrl.2", .fops = &penctrl_fops },
+ { .minor = 3, .name = "penctrl.3", .fops = &penctrl_fops },
+};
+
+static int penctrl_spi_probe(struct spi_device *spi)
+{
+ int i, ret;
+
+ /* Allocate driver data */
+ penctrl = kzalloc(sizeof(*penctrl), GFP_KERNEL);
+ if (!penctrl)
+ return -ENOMEM;
+
+ penctrl->spi = spi;
+ mutex_init(&spi_lock);
+
+ for (i = 0; i < ARRAY_SIZE(penctrl_devices); i++) {
+ ret = misc_register(&penctrl_devices[i]);
+ if (ret) {
+ dev_err(&spi->dev, "Failed to register device %s\n",
+ penctrl_devices[i].name);
+ goto cleanup;
+ }
+ }
+
+ /* Register reset controller */
+ penctrl->rcdev.dev = &spi->dev;
+ penctrl->rcdev.ops = &penctrl_reset_ops;
+ penctrl->rcdev.owner = THIS_MODULE;
+ penctrl->rcdev.of_node = spi->dev.of_node;
+ penctrl->rcdev.nr_resets = 1;
+ device_set_node(penctrl->rcdev.dev, dev_fwnode(&spi->dev));
+
+ ret = reset_controller_register(&penctrl->rcdev);
+ if (ret)
+ return dev_err_probe(&spi->dev, ret,
+ "failed to register reset controller\n");
+ return 0;
+
+cleanup:
+ for (i = 0; i < ARRAY_SIZE(penctrl_devices); i++) {
+ if (penctrl_devices[i].this_device)
+ misc_deregister(&penctrl_devices[i]);
+ }
+ return ret;
+}
+
+static const struct of_device_id penctrl_dt_match[] = {
+ { .compatible = "amd,pensando-elba-ctrl" },
+ { /* sentinel */ }
+};
+
+static struct spi_driver penctrl_spi_driver = {
+ .probe = penctrl_spi_probe,
+ .driver = {
+ .name = "pensando-elba-ctrl",
+ .of_match_table = penctrl_dt_match,
+ },
+};
+module_spi_driver(penctrl_spi_driver);
+
+MODULE_AUTHOR("Brad Larson <blarson@amd.com>");
+MODULE_DESCRIPTION("AMD Pensando SoC Controller via SPI");
+MODULE_LICENSE("GPL");
new file mode 100644
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Userspace interface for /dev/penctrl
+ *
+ * This file can be used by applications that need to communicate
+ * with the AMD Pensando SoC controller device via the ioctl interface.
+ */
+#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H
+#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H
+
+#include <linux/types.h>
+
+#define PENCTRL_SPI_CMD_REGRD 0x0b
+#define PENCTRL_SPI_CMD_REGWR 0x02
+#define PENCTRL_MAX_MSG_LEN 16
+#define PENCTRL_MAX_REG 0xff
+#define PENCTRL_REG_CTRL0 0x10
+
+struct penctrl_spi_xfer {
+ __u64 tx_buf;
+ __u64 rx_buf;
+ __u32 len;
+ __u32 speed_hz;
+ __u64 compat;
+};
+
+#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */
The Pensando SoC controller is a SPI connected companion device that is present in all Pensando SoC board designs. The essential board management registers are accessed on chip select 0 with board mgmt IO support accessed using additional chip selects. Signed-off-by: Brad Larson <blarson@amd.com> --- v15 changes: - Drop custom ioctl and use existing miscdevice interface. - Makefile change to only compile for ARCH_PENSANDO v14 changes: - Save 8 bytes of code size by swapping spi_device and reset_controller_dev in penctrl_device - Code simplification and clarity from review inputs - Set penctrl_spi_driver.driver.name to match compatible pensando-elba-ctrl - Remove unused include in amd-pensando-ctrl.h - Rebase to linux-next 6.4.0-rc1 class_create() API change v13 changes: - Update include list in pensando-ctrl.c - Change variable spi_dev to spi throughout - Removed unneeded variable initialization, simplification of error checks, remove extra castings, and use dev_err_probe() - Sort the includes in amd-pensando-ctrl.h - Updates to cleanup if there is an error in penctrl_spi_probe() v12 changes: - Fix gcc-12.1.0 warning v11 changes: - Fix the compatible to be specific 'amd,pensando-elba-ctrl' v10 changes: - Different driver implementation specific to this Pensando controller device. - Moved to soc/amd directory under new name based on guidance. This driver is of no use to any design other than all Pensando SoC based cards. - Removed use of builtin_driver, can be built as a module. v9 changes: - Previously patch 14/17 - After the change to the device tree node and squashing reset-cells into the parent simplified this to not use any MFD API and move it to drivers/spi/pensando-sr.c. - Change the naming to remove elba since this driver is common for all Pensando SoC designs . - Default yes SPI_PENSANDO_SR for ARCH_PENSANDO --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/amd/Kconfig | 16 ++ drivers/soc/amd/Makefile | 2 + drivers/soc/amd/pensando-ctrl.c | 311 +++++++++++++++++++++++++ include/uapi/linux/amd-pensando-ctrl.h | 27 +++ 6 files changed, 358 insertions(+) create mode 100644 drivers/soc/amd/Kconfig create mode 100644 drivers/soc/amd/Makefile create mode 100644 drivers/soc/amd/pensando-ctrl.c create mode 100644 include/uapi/linux/amd-pensando-ctrl.h