From patchwork Fri Jun 7 15:18:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Witold Sadowski X-Patchwork-Id: 13690380 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B381615B133; Fri, 7 Jun 2024 15:18:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717773523; cv=none; b=bQ0zhDCRFd5UYqFZyMMveoqVoVqfNbKQtnEB0DtY68M3+qgk+IL6+6ituLMfy+PYiFXyyz2vJKL4dkvc6PbFwn344iz5s625C14N05oCu1ql08flzV3/95pfeBlN4G9iZIhYg3Ql0DvEiCbtKOkuSOu203GWImKD1dsd5qB7ZAY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717773523; c=relaxed/simple; bh=cHicvuNsB6FBsP+p24Oei7cf3LE105dI1jDELbVa/L8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qp4Ka2B6FVMinIaGjMnoUVnM2DGfO+XjHTphay12DdmebXnfZA4ASs7DDhMqSeVOR1Y2kYIgawTUzkomIWj4MD50Ejx3/Vvm02+IqXMdm6GMkOC58XOGex1+DPtEuWeeenlEBWBUxnMEYJDfOnZXHF0ddiaT+W0zrV1lNZEVEGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=JK9nUzKZ; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="JK9nUzKZ" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 457AErQ2014896; Fri, 7 Jun 2024 08:18:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=q HWv3FV88gHLyPrpIGGB1AAf2zkoSjgvgaCyZbzsiAY=; b=JK9nUzKZT82UeZPPF Aghut2iUYcMiCXBLaxPgk0sFOj2f1wOSRJlf8Bm7iGmmaHXz87AHYDMg8fG4L0kr 2BOVZqMRykw1NNkxzwyxLwpfbujtKTEnhCJ4ZMkm3Bf1iE7axrkRovczZT3CJIem AlXWg+11gAGXv59Cj075qlrL97nBE/Z79PKA+hmnnPgqR4j/f4xQBceXNScKxm2V MkDbk6vkOhSopatD0msJFsdE8cZ9EyWLj0HwjfOuwF6BLXKmpBZ8TaCmNSk19Eul FIb0Q0W26TOHU9kWCd+lNf0cJUo1nCHoAT3S2DvEoExp28iWT7OQzwX98IbJjoxO 79Ocg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ym09ngx2t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Jun 2024 08:18:36 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 7 Jun 2024 08:18:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 7 Jun 2024 08:18:35 -0700 Received: from Dell2s-9.sclab.marvell.com (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 6D5443F7097; Fri, 7 Jun 2024 08:18:35 -0700 (PDT) From: Witold Sadowski To: , , CC: , , , , , Witold Sadowski , "Krzysztof Kozlowski" Subject: [PATCH v8 1/4] spi: dt-bindings: cadence: Add Marvell overlay bindings documentation for Cadence XSPI Date: Fri, 7 Jun 2024 08:18:28 -0700 Message-ID: <20240607151831.3858304-2-wsadowski@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240607151831.3858304-1-wsadowski@marvell.com> References: <20240607151831.3858304-1-wsadowski@marvell.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: -pPalRsH_V91tp1wSFGpPqfKhDs7CdPq X-Proofpoint-ORIG-GUID: -pPalRsH_V91tp1wSFGpPqfKhDs7CdPq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_09,2024-06-06_02,2024-05-17_01 Add new bindings for the v2 Marvell xSPI overlay: marvell,cn10-xspi-nor compatible string. This new compatible string distinguishes between the original and modified xSPI block. Also add an optional base for the xfer register set with an additional reg field to allocate the xSPI Marvell overlay XFER block. Signed-off-by: Witold Sadowski Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/spi/cdns,xspi.yaml | 32 ++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml index eb0f92468185..38a5795589de 100644 --- a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml @@ -15,24 +15,27 @@ description: | single, dual, quad or octal wire transmission modes for read/write access to slaves such as SPI-NOR flash. -allOf: - - $ref: spi-controller.yaml# - properties: compatible: - const: cdns,xspi-nor + enum: + - cdns,xspi-nor + - marvell,cn10-xspi-nor reg: items: - description: address and length of the controller register set - description: address and length of the Slave DMA data port - description: address and length of the auxiliary registers + - description: address and length of the xfer registers + minItems: 3 reg-names: items: - const: io - const: sdma - const: aux + - const: xfer + minItems: 3 interrupts: maxItems: 1 @@ -42,6 +45,27 @@ required: - reg - interrupts +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - marvell,cn10-xspi-nor + then: + properties: + reg: + minItems: 4 + reg-names: + minItems: 4 + else: + properties: + reg: + maxItems: 3 + reg-names: + maxItems: 3 + unevaluatedProperties: false examples: