From patchwork Mon Jul 29 08:43:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Usyskin, Alexander" X-Patchwork-Id: 13744592 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CD8B139D12 for ; Mon, 29 Jul 2024 08:52:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722243123; cv=none; b=iMXlV2KGZOp7KnD3Pgyps0yzr2jR070YEr4W/DwJ+excE9wVBeJg33YdRHoTIayqGS/ppnnVFG9hVoU7SNohXa3DwenX0tY/O4Zg7O6j49bZmBVE10UKxA3DPLk4/bdVfgmRhebagvauVETN3JR7kcN5y6PfsA4hJu20zceA/48= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722243123; c=relaxed/simple; bh=1PgtufbKR7hYf05j8MjxBNN0ilzMGaZeL81os+nmGXc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XnhirAcRUXY/FE0QaN9BUbxMcMxIwPfATnZjY0KDgV+kKoUgutZRMez9x1Jr1JpTbCIethm5UnMf1Sv00V0T2wuqYb0D/45OfgcHyu2IASMbGNZQ8YynEur1a6iVHcU3c0QRJQO21uGbZJWxD3T4e0wOhU6yErufzRlM1+zVf8Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cnM9wEv9; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cnM9wEv9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722243121; x=1753779121; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1PgtufbKR7hYf05j8MjxBNN0ilzMGaZeL81os+nmGXc=; b=cnM9wEv9AW54htMMqON63debF4xSAHeTJW+88sadFCE1ZQcsx7uD/3K5 07nI50Kk3ie7jA7zUTW/4GOL1mZNaQ9LIwMVm/SyZWYnQYnBs4K+Rlyhg gSJOH/eeZH7fdr8lWKqiFePI1eH008iKEX9/2pHyjGpyuhkLkPvqi/BR6 gNMg6gEF5VOOFfQX3OGC1He8tw2iYUhuFEhFWGjZh8SXdnWwa7YEMRMbH TasJ8XN4YwHsW8hDve5hoUwH9aQ2UMCCNPmi8pcjgFKmLbW9ZPfLvmAgA 90X3ggf4i+kAEZZ2U0GKUIZ1VDadmGq3tHsGEVgJ2gL7rz7xG0GRsJZlr A==; X-CSE-ConnectionGUID: urPWfz+VRv+bvvtXPhKn1A== X-CSE-MsgGUID: fo2TyvKoTDeUQYrFty6hKQ== X-IronPort-AV: E=McAfee;i="6700,10204,11147"; a="42508959" X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="42508959" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2024 01:52:01 -0700 X-CSE-ConnectionGUID: Nk/+S97rRc+Y4kqeskO8kA== X-CSE-MsgGUID: 0R3RcNekR22pyxuPlRffpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,245,1716274800"; d="scan'208";a="54708277" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2024 01:51:56 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v5 02/12] spi: intel-dg: implement region enumeration Date: Mon, 29 Jul 2024 11:43:16 +0300 Message-Id: <20240729084326.2278014-3-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240729084326.2278014-1-alexander.usyskin@intel.com> References: <20240729084326.2278014-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Tomas Winkler In intel-dg spi, there is no access to the spi controller, the information is extracted from the descriptor region. CC: Rodrigo Vivi CC: Lucas De Marchi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/spi/spi-intel-dg.c | 190 +++++++++++++++++++++++++++++++++++++ 1 file changed, 190 insertions(+) diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c index 4e302957f077..661e5189fa58 100644 --- a/drivers/spi/spi-intel-dg.c +++ b/drivers/spi/spi-intel-dg.c @@ -17,14 +17,197 @@ struct intel_dg_spi { void __iomem *base; size_t size; unsigned int nregions; + u32 access_map; struct { const char *name; u8 id; u64 offset; u64 size; + unsigned int is_readable:1; + unsigned int is_writable:1; } regions[]; }; +#define SPI_TRIGGER_REG 0x00000000 +#define SPI_VALSIG_REG 0x00000010 +#define SPI_ADDRESS_REG 0x00000040 +#define SPI_REGION_ID_REG 0x00000044 +/* + * [15:0]-Erase size = 0x0010 4K 0x0080 32K 0x0100 64K + * [23:16]-Reserved + * [31:24]-Erase SPI RegionID + */ +#define SPI_ERASE_REG 0x00000048 +#define SPI_ACCESS_ERROR_REG 0x00000070 +#define SPI_ADDRESS_ERROR_REG 0x00000074 + +/* Flash Valid Signature */ +#define SPI_FLVALSIG 0x0FF0A55A + +#define SPI_MAP_ADDR_MASK 0x000000FF +#define SPI_MAP_ADDR_SHIFT 0x00000004 + +#define REGION_ID_DESCRIPTOR 0 +/* Flash Region Base Address */ +#define FRBA 0x40 +/* Flash Region __n - Flash Descriptor Record */ +#define FLREG(__n) (FRBA + ((__n) * 4)) +/* Flash Map 1 Register */ +#define FLMAP1_REG 0x18 +#define FLMSTR4_OFFSET 0x00C + +#define SPI_ACCESS_ERROR_PCIE_MASK 0x7 + +static inline void spi_set_region_id(struct intel_dg_spi *spi, u8 region) +{ + iowrite32((u32)region, spi->base + SPI_REGION_ID_REG); +} + +static inline u32 spi_error(struct intel_dg_spi *spi) +{ + u32 reg = ioread32(spi->base + SPI_ACCESS_ERROR_REG) & + SPI_ACCESS_ERROR_PCIE_MASK; + + /* reset error bits */ + if (reg) + iowrite32(reg, spi->base + SPI_ACCESS_ERROR_REG); + + return reg; +} + +static inline u32 spi_read32(struct intel_dg_spi *spi, u32 address) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + return ioread32(base + SPI_TRIGGER_REG); +} + +static int spi_get_access_map(struct intel_dg_spi *spi) +{ + u32 flmap1; + u32 fmba; + u32 fmstr4; + u32 fmstr4_addr; + + spi_set_region_id(spi, REGION_ID_DESCRIPTOR); + + flmap1 = spi_read32(spi, FLMAP1_REG); + if (spi_error(spi)) + return -EIO; + /* Get Flash Master Baser Address (FMBA) */ + fmba = ((flmap1 & SPI_MAP_ADDR_MASK) << SPI_MAP_ADDR_SHIFT); + fmstr4_addr = fmba + FLMSTR4_OFFSET; + + fmstr4 = spi_read32(spi, fmstr4_addr); + if (spi_error(spi)) + return -EIO; + + spi->access_map = fmstr4; + return 0; +} + +static bool spi_region_readable(struct intel_dg_spi *spi, u8 region) +{ + if (region < 12) + return spi->access_map & (1 << (region + 8)); /* [19:8] */ + else + return spi->access_map & (1 << (region - 12)); /* [3:0] */ +} + +static bool spi_region_writeable(struct intel_dg_spi *spi, u8 region) +{ + if (region < 12) + return spi->access_map & (1 << (region + 20)); /* [31:20] */ + else + return spi->access_map & (1 << (region - 8)); /* [7:4] */ +} + +static int intel_dg_spi_is_valid(struct intel_dg_spi *spi) +{ + u32 is_valid; + + spi_set_region_id(spi, REGION_ID_DESCRIPTOR); + + is_valid = spi_read32(spi, SPI_VALSIG_REG); + if (spi_error(spi)) + return -EIO; + + if (is_valid != SPI_FLVALSIG) + return -ENODEV; + + return 0; +} + +static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device) +{ + int ret; + unsigned int i, n; + + /* clean error register, previous errors are ignored */ + spi_error(spi); + + ret = intel_dg_spi_is_valid(spi); + if (ret) { + dev_err(device, "The SPI is not valid %d\n", ret); + return ret; + } + + if (spi_get_access_map(spi)) + return -EIO; + + for (i = 0, n = 0; i < spi->nregions; i++) { + u32 address, base, limit, region; + u8 id = spi->regions[i].id; + + address = FLREG(id); + region = spi_read32(spi, address); + + base = (region & 0x0000FFFF) << 12; + limit = (((region & 0xFFFF0000) >> 16) << 12) | 0xFFF; + + dev_dbg(device, "[%d] %s: region: 0x%08X base: 0x%08x limit: 0x%08x\n", + id, spi->regions[i].name, region, base, limit); + + if (base >= limit || (i > 0 && limit == 0)) { + dev_dbg(device, "[%d] %s: disabled\n", + id, spi->regions[i].name); + spi->regions[i].is_readable = 0; + continue; + } + + if (spi->size < limit) + spi->size = limit; + + spi->regions[i].offset = base; + spi->regions[i].size = limit - base + 1; + /* No write access to descriptor; mask it out*/ + spi->regions[i].is_writable = spi_region_writeable(spi, id); + + spi->regions[i].is_readable = spi_region_readable(spi, id); + dev_dbg(device, "Registered, %s id=%d offset=%lld size=%lld rd=%d wr=%d\n", + spi->regions[i].name, + spi->regions[i].id, + spi->regions[i].offset, + spi->regions[i].size, + spi->regions[i].is_readable, + spi->regions[i].is_writable); + + if (spi->regions[i].is_readable) + n++; + } + + dev_dbg(device, "Registered %d regions\n", n); + + /* Need to add 1 to the amount of memory + * so it is reported as an even block + */ + spi->size += 1; + + return n; +} + static void intel_dg_spi_release(struct kref *kref) { struct intel_dg_spi *spi = container_of(kref, struct intel_dg_spi, refcnt); @@ -92,6 +275,13 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev, goto err; } + ret = intel_dg_spi_init(spi, device); + if (ret < 0) { + dev_err(device, "cannot initialize spi\n"); + ret = -ENODEV; + goto err; + } + dev_set_drvdata(&aux_dev->dev, spi); return 0;