From patchwork Mon Sep 16 13:49:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Usyskin, Alexander" X-Patchwork-Id: 13805517 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 438B515B104 for ; Mon, 16 Sep 2024 13:58:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726495140; cv=none; b=ZikJnWWdAl2WJvibm5Os3JH2qFrj8gwEgKAmHHWpHlWTlA6avGy1FoLTMimHMGu/CaJh79LEjo91LKRinwK/sxTvwhMDiGHo2J5nM8x/+DwfyVgf3f9XPaB8DOI3xqjXm4eaMc3ktXLD/H4YuAw3nsrNL2QrcONai5GHT/N0Ibo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726495140; c=relaxed/simple; bh=XwjfPtNKP3xj4mYiGTP+Pjdqb0DSUXkzIDtfWZSx5QA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Oscc48OoSt+oVAGxTObU/+hgFPNPhyKc9kqPjrj6+ZdtbeTBDF1odkyKK75LjK3aOc39/CTxfjpCZM3auH+2Qar7AxpVdcpY3+NzJWT2HRmpPMETwH/4SQJG15U5h3OWDDk8hqjnuCl71S9SGWNFHCqkfrq7lh63Go3hoTFuQcU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GAlt2eum; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GAlt2eum" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726495139; x=1758031139; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XwjfPtNKP3xj4mYiGTP+Pjdqb0DSUXkzIDtfWZSx5QA=; b=GAlt2eumzZzQArCQ/kxEace33W/U7yNKoSF3CdxSoKQeH0qPKTz6aUGG VrY+Y/7HkV3XH3bvmn+mIMFxThoQ3+uwexhUlkEBIh0SW//6swmGus+No ClYh4kequI2EAK3W0uw0iZni74fQKhcsGxfMN5PNKudjMVR0s9A0EqG+n 7y5TemdGr/WIEvNpm9vOacKa12JPcqW73zo36hpeiND97BBqHMzlA1UmN gSNq9gf+19xkTUr2psI8xc2XfxPlIvKvcdnaOWmbO4dC8OOWY9QkC8kIO Ecz0s8HCfSxMMfVhicoZBB++PND2NR+rUQPCrIy0QW1JnNse9SaaKmjur A==; X-CSE-ConnectionGUID: 4qx/sHZLSz2Wc/Q0C2NQuQ== X-CSE-MsgGUID: sIHGQo6SR1SGyz5CYxyp6Q== X-IronPort-AV: E=McAfee;i="6700,10204,11197"; a="36666897" X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="36666897" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:58:12 -0700 X-CSE-ConnectionGUID: 2veiaqVQRSezaq52EQaNLQ== X-CSE-MsgGUID: wmGrMlcLSc6g4I8AYGZDbA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="68837453" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:58:08 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v6 09/12] drm/i915/spi: add intel_spi_region map Date: Mon, 16 Sep 2024 16:49:25 +0300 Message-Id: <20240916134928.3654054-10-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916134928.3654054-1-alexander.usyskin@intel.com> References: <20240916134928.3654054-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Tomas Winkler Add the dGFX spi region map and convey it via auxiliary device to the spi child device. CC: Rodrigo Vivi CC: Lucas De Marchi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/spi/intel_spi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c index 4b90e42b0f86..200139531d26 100644 --- a/drivers/gpu/drm/i915/spi/intel_spi.c +++ b/drivers/gpu/drm/i915/spi/intel_spi.c @@ -11,6 +11,13 @@ #define GEN12_GUNIT_SPI_SIZE 0x80 +static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = { + [0] = { .name = "DESCRIPTOR", }, + [2] = { .name = "GSC", }, + [11] = { .name = "OptionROM", }, + [12] = { .name = "DAM", }, +}; + static void i915_spi_release_dev(struct device *dev) { } @@ -31,6 +38,7 @@ void intel_spi_init(struct drm_i915_private *dev_priv) spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1; spi->bar.flags = IORESOURCE_MEM; spi->bar.desc = IORES_DESC_NONE; + spi->regions = regions; aux_dev->name = "spi"; aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |