From patchwork Mon Sep 16 13:49:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 13805516 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29CAA15ADB8 for ; Mon, 16 Sep 2024 13:58:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726495139; cv=none; b=cd28PdKSKX70eZDGRjl2jcvY8kDY1UW9ZiVuuHilMxac20rIBb18VGsafDmslTljT1pO1+uiNhaJ5OXv/oTwdLpKlF3rwxbs4nZwA9Ip2Y/vfDc6UF3P0KMBE5wn8ES64FyWbGkhdY8TCQ/9C3PGrysxxWBFbtb/dobXptr84xg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726495139; c=relaxed/simple; bh=B99SUdIMw00Q3to8mLhSTBkkBU3L+khmykvel5CmBuo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RPBLewwPfpY7lc1bKDdF4TeyJ6kYAA1iKjhSqX6wuJDKoMSoIWqUmSF9vN8LDciZKEG970bRg8pCGqHaz7/c4rtljVK22G/B/8dGwGN2LeRlgpwjNoFrVZVb6ruKNQP9k41yPKLR+FONJLWwCH8njcwlcg2pCdV+8F6xcHLVoCs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TGA68aDU; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TGA68aDU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726495138; x=1758031138; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B99SUdIMw00Q3to8mLhSTBkkBU3L+khmykvel5CmBuo=; b=TGA68aDU7pMAvXtJXeEHOo/4Bcr38vhA584cZYXMveQxgTWucLuNDsxY LGvjCHeHNaFQae2s57K84DyU0IEOBx57SczL6hGnVz2rlWPO7eFp0Rj41 g9+mQTnMkPgplQsIH6wBF6KtvwvaPWNeOQRHpbt3W4e4HA7JIcUt9Jw0n 2WGwrLsjTpL0pbwQ5RqGjXO4TAMfde9v3bF9uR1VsaK18h/z+ppiq3ZUd /rNEKpLzJYAyFxkCRfO+wjRwY87UooZPaXdn4S0qoBiSPOUqjKd7nPK4E 1J32JSWF50h8NMi7BwHE4vwIux+ICGCjk8r8Cwgfy4w2IvXzjDCBwOqfc Q==; X-CSE-ConnectionGUID: n79PO7rIQF2EXiF8Ag8NFA== X-CSE-MsgGUID: xnrZ3pZ3SsaKffGxDpNCrg== X-IronPort-AV: E=McAfee;i="6700,10204,11197"; a="36666881" X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="36666881" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:58:07 -0700 X-CSE-ConnectionGUID: TIuY0X+NRHC6FXDtEKznDA== X-CSE-MsgGUID: 3XEZIT1ISY2VQNEHoue6ng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="68837429" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2024 06:58:02 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v6 08/12] drm/i915/spi: add spi device for discrete graphics Date: Mon, 16 Sep 2024 16:49:24 +0300 Message-Id: <20240916134928.3654054-9-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916134928.3654054-1-alexander.usyskin@intel.com> References: <20240916134928.3654054-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Tomas Winkler Enable access to internal spi on DGFX devices via a child device. The spi child device is exposed via auxiliary bus. CC: Rodrigo Vivi CC: Lucas De Marchi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/Makefile | 4 ++ drivers/gpu/drm/i915/i915_driver.c | 6 +++ drivers/gpu/drm/i915/i915_drv.h | 4 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/spi/intel_spi.c | 68 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/spi/intel_spi.h | 15 ++++++ 6 files changed, 98 insertions(+) create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index c63fa2133ccb..02a9faf049a7 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -211,6 +211,10 @@ i915-y += \ i915-y += \ gt/intel_gsc.o +# graphics spi device (DGFX) support +i915-y += \ + spi/intel_spi.o + # graphics hardware monitoring (HWMON) support i915-$(CONFIG_HWMON) += \ i915_hwmon.o diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index fe905d65ddf7..80330571a2f5 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -80,6 +80,8 @@ #include "soc/intel_dram.h" #include "soc/intel_gmch.h" +#include "spi/intel_spi.h" + #include "i915_debugfs.h" #include "i915_driver.h" #include "i915_drm_client.h" @@ -620,6 +622,8 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) /* Depends on sysfs having been initialized */ i915_perf_register(dev_priv); + intel_spi_init(dev_priv); + for_each_gt(gt, dev_priv, i) intel_gt_driver_register(gt); @@ -663,6 +667,8 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) i915_hwmon_unregister(dev_priv); + intel_spi_fini(dev_priv); + i915_perf_unregister(dev_priv); i915_pmu_unregister(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 39f6614a0a99..b9d4f9be5355 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -34,6 +34,8 @@ #include +#include + #include #include "display/intel_display_limits.h" @@ -315,6 +317,8 @@ struct drm_i915_private { struct i915_perf perf; + struct intel_dg_spi_dev spi; + struct i915_hwmon *hwmon; struct intel_gt *gt[I915_MAX_GT]; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 41f4350a7c6c..af5d0497b95c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -323,6 +323,7 @@ #define DG2_GSC_HECI2_BASE 0x00374000 #define MTL_GSC_HECI1_BASE 0x00116000 #define MTL_GSC_HECI2_BASE 0x00117000 +#define GEN12_GUNIT_SPI_BASE 0x00102040 #define HECI_H_CSR(base) _MMIO((base) + 0x4) #define HECI_H_CSR_IE REG_BIT(0) diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c new file mode 100644 index 000000000000..4b90e42b0f86 --- /dev/null +++ b/drivers/gpu/drm/i915/spi/intel_spi.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. + */ + +#include +#include +#include "i915_reg.h" +#include "i915_drv.h" +#include "spi/intel_spi.h" + +#define GEN12_GUNIT_SPI_SIZE 0x80 + +static void i915_spi_release_dev(struct device *dev) +{ +} + +void intel_spi_init(struct drm_i915_private *dev_priv) +{ + struct intel_dg_spi_dev *spi = &dev_priv->spi; + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + struct auxiliary_device *aux_dev = &spi->aux_dev; + int ret; + + /* Only the DGFX devices have internal SPI */ + if (!IS_DGFX(dev_priv)) + return; + + spi->bar.parent = &pdev->resource[0]; + spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start; + spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1; + spi->bar.flags = IORESOURCE_MEM; + spi->bar.desc = IORES_DESC_NONE; + + aux_dev->name = "spi"; + aux_dev->id = (pci_domain_nr(pdev->bus) << 16) | + PCI_DEVID(pdev->bus->number, pdev->devfn); + aux_dev->dev.parent = &pdev->dev; + aux_dev->dev.release = i915_spi_release_dev; + + ret = auxiliary_device_init(aux_dev); + if (ret) { + dev_err(&pdev->dev, "i915-spi aux init failed %d\n", ret); + return; + } + + ret = auxiliary_device_add(aux_dev); + if (ret) { + dev_err(&pdev->dev, "i915-spi aux add failed %d\n", ret); + auxiliary_device_uninit(aux_dev); + return; + } +} + +void intel_spi_fini(struct drm_i915_private *dev_priv) +{ + struct intel_dg_spi_dev *spi = &dev_priv->spi; + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + + /* Only the DGFX devices have internal SPI */ + if (!IS_DGFX(dev_priv)) + return; + + dev_dbg(&pdev->dev, "removing i915-spi cell\n"); + + auxiliary_device_delete(&spi->aux_dev); + auxiliary_device_uninit(&spi->aux_dev); +} diff --git a/drivers/gpu/drm/i915/spi/intel_spi.h b/drivers/gpu/drm/i915/spi/intel_spi.h new file mode 100644 index 000000000000..ed4153401f5d --- /dev/null +++ b/drivers/gpu/drm/i915/spi/intel_spi.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2019-2024 Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_SPI_H__ +#define __INTEL_SPI_H__ + +struct drm_i915_private; + +void intel_spi_init(struct drm_i915_private *i915); + +void intel_spi_fini(struct drm_i915_private *i915); + +#endif /* __INTEL_SPI_H__ */