| Message ID | 20240922113351.2390195-2-quic_mdalam@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add QPIC SPI NAND driver | expand |
On Sun, Sep 22, 2024 at 05:03:44PM +0530, Md Sadre Alam wrote: > Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. > It can work both in serial and parallel mode and supports typical > SPI-NAND page cache operations. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> > --- > > Change in [v10] > > * No change ... > +title: Qualcomm QPIC NAND controller > + > +maintainers: > + - Md sadre Alam <quic_mdalam@quicinc.com> > + > +description: > + The QCOM QPIC-SPI-NAND flash controller is an extended version of > + the QCOM QPIC NAND flash controller. It can work both in serial > + and parallel mode. It supports typical SPI-NAND page cache > + operations in single, dual or quad IO mode with pipelined ECC > + encoding/decoding using the QPIC ECC HW engine. > + > +allOf: > + - $ref: /schemas/spi/spi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - qcom,spi-qpic-snand Recently it turned out that Qualcomm generic compatibles are not generic... That was odd, but to me it is a clear signal that something should not be called generic if it is not generic enough. Please switch to soc-specific compatibles (and drop my reviewed-by, so this will appear in my review queue). Best regards, Krzysztof
On 9/23/2024 2:02 AM, Krzysztof Kozlowski wrote: > On Sun, Sep 22, 2024 at 05:03:44PM +0530, Md Sadre Alam wrote: >> Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. >> It can work both in serial and parallel mode and supports typical >> SPI-NAND page cache operations. >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> >> --- >> >> Change in [v10] >> >> * No change > > ... > >> +title: Qualcomm QPIC NAND controller >> + >> +maintainers: >> + - Md sadre Alam <quic_mdalam@quicinc.com> >> + >> +description: >> + The QCOM QPIC-SPI-NAND flash controller is an extended version of >> + the QCOM QPIC NAND flash controller. It can work both in serial >> + and parallel mode. It supports typical SPI-NAND page cache >> + operations in single, dual or quad IO mode with pipelined ECC >> + encoding/decoding using the QPIC ECC HW engine. >> + >> +allOf: >> + - $ref: /schemas/spi/spi-controller.yaml# >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,spi-qpic-snand > > Recently it turned out that Qualcomm generic compatibles are not > generic... That was odd, but to me it is a clear signal that something > should not be called generic if it is not generic enough. > > Please switch to soc-specific compatibles (and drop my reviewed-by, so > this will appear in my review queue). Ok , will add in next revision. > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml new file mode 100644 index 000000000000..f0d9f7643849 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QPIC NAND controller + +maintainers: + - Md sadre Alam <quic_mdalam@quicinc.com> + +description: + The QCOM QPIC-SPI-NAND flash controller is an extended version of + the QCOM QPIC NAND flash controller. It can work both in serial + and parallel mode. It supports typical SPI-NAND page cache + operations in single, dual or quad IO mode with pipelined ECC + encoding/decoding using the QPIC ECC HW engine. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - qcom,spi-qpic-snand + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: core + - const: aon + - const: iom + + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + - description: cmd DMA channel + + dma-names: + items: + - const: tx + - const: rx + - const: cmd + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> + spi@79b0000 { + compatible = "qcom,spi-qpic-snand"; + reg = <0x1ac00000 0x800>; + + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", "aon", "iom"; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; + };