Message ID | 20240923044543.2222-1-amit.kumar-mahapatra@amd.com (mailing list archive) |
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dt-bindings: spi: zynqmp-qspi: Include two 'reg' properties only for the Zynq UltraScale QSPI
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diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index e5199b109dad..2f1fca137cd3 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -12,15 +12,27 @@ maintainers: allOf: - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: xlnx,zynqmp-qspi-1.0 + then: + properties: + reg: + maxItems: 2 + + else: + properties: + reg: + maxItems: 1 + properties: compatible: enum: - xlnx,versal-qspi-1.0 - xlnx,zynqmp-qspi-1.0 - reg: - maxItems: 2 - interrupts: maxItems: 1
Linear mode is only supported by the Zynq UltraScale QSPI controller, so update the bindings to include two 'reg' properties only for the Zynq UltraScale QSPI controller. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> --- BRANCH: for-next --- .../bindings/spi/spi-zynqmp-qspi.yaml | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)