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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F3.mail.protection.outlook.com (10.167.241.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Mon, 23 Sep 2024 12:32:50 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 23 Sep 2024 07:32:48 -0500 Received: from xhdakumarma40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Mon, 23 Sep 2024 07:32:44 -0500 From: Amit Kumar Mahapatra To: , , , CC: , , , , , , , Amit Kumar Mahapatra Subject: [PATCH] dt-bindings: spi: xilinx: Add clocks & clock-names properties Date: Mon, 23 Sep 2024 18:02:42 +0530 Message-ID: <20240923123242.2101562-1-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: amit.kumar-mahapatra@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F3:EE_|SA1PR12MB6893:EE_ X-MS-Office365-Filtering-Correlation-Id: c62ad539-2d5e-43f5-1567-08dcdbcbd691 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2024 12:32:50.2569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c62ad539-2d5e-43f5-1567-08dcdbcbd691 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6893 Include the 'clocks' and 'clock-names' properties in the AXI Quad-SPI bindings. When the AXI4-Lite interface is enabled, the core operates in legacy mode, maintaining backward compatibility with version 1.00, and uses 's_axi_aclk' and 'ext_spi_clk'. For the AXI interface, it uses 's_axi4_aclk' and 'ext_spi_clk'. Signed-off-by: Amit Kumar Mahapatra --- BRANCH: for-next --- .../devicetree/bindings/spi/spi-xilinx.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml index 4beb3af0416d..9dfec195ecd4 100644 --- a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml @@ -12,6 +12,25 @@ maintainers: allOf: - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: xlnx,axi-quad-spi-1.00.a + then: + properties: + clock-names: + items: + - const: s_axi_aclk + - const: ext_spi_clk + + else: + properties: + clock-names: + items: + - const: s_axi4_aclk + - const: ext_spi_clk + properties: compatible: enum: @@ -25,6 +44,12 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + xlnx,num-ss-bits: description: Number of chip selects used. minimum: 1 @@ -39,6 +64,8 @@ required: - compatible - reg - interrupts + - clocks + - clock-names unevaluatedProperties: false @@ -49,6 +76,8 @@ examples: interrupt-parent = <&intc>; interrupts = <0 31 1>; reg = <0x41e00000 0x10000>; + clocks = <&clkc 72>, <&clkc 73>; + clock-names = "s_axi4_aclk", "ext_spi_clk"; xlnx,num-ss-bits = <0x1>; xlnx,num-transfer-bits = <32>; };