From patchwork Fri Oct 25 16:14:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13851048 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57DB17082B for ; Fri, 25 Oct 2024 16:15:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729872920; cv=none; b=AMAgWVOW1+w5hUvLU3G+2atYqM8Z4ziQeOZqXOHNZbd5MAA25HsRJ6bpsKMUIi6yoglfA0vhAFfGgYNizefL74TQc8t2AUD4cAtR4v57FyomRI7L/CSuoqyx20y+jdc8pUyck5sBGMCxWOt6L5MTAql3MXAk5vdl/DgerYFZpVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729872920; c=relaxed/simple; bh=Qfo7MvBGSSwqATFep9wNO1AlzZYnF2jQLkVXSNQV8cg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ChvdjvB5cNHh11K/SXF5ZByOu1h6Em2moEM+bN8EFT4q0xrRaR0pBShabcEZX9t9xl8EIlX//Q6GMYTcql/M1cZFhdieKnn5uL7IByAyVEtp5v9ZXRQfWT0pI3m+bIF5tVnIWGAY/oQaNNeAveLb27vgWMVPiFirJONHqXli5mM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=GWysGgJF; arc=none smtp.client-ip=217.70.183.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="GWysGgJF" Received: by mail.gandi.net (Postfix) with ESMTPSA id 07544E0004; Fri, 25 Oct 2024 16:15:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1729872917; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dHmHTREvtaKp6LdBhOuS0MhsikSE6cns2etQNgpEJaA=; b=GWysGgJFc7vF8n7eNSaeEF2i9Z6ZpTz9TM7k8/3B8GsygqjDBShYXF3O/77H8YeazTpJeh VqRotpt67XeMozgcIW+kzoC6Gd58z5NJRmR1Q9rfBskaDEhtTsmGWMybmGKSxDYWtB646l ulUxpuAghbC2V4hjPyDTymQD68yGIkkyeS84wk9ch2QLeTmTQGAW5nibDyuVAS0Q7vCYmg 2FAVWBlstt3WHBAuxHc2uTaDBVOQ3WqgHPwhnz4GuIEIwyAdxP0gNJuCkxhRrHnUXBfQKm dYDOah906AeBEJ6C3PBrbf0JwD+FSw3ya0i4CRSrFkVQFlmHaQGSrKK77/Mwrg== From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: Mark Brown , , Steam Lin , Thomas Petazzoni , Sanjay R Mehta , Han Xu , Conor Dooley , Daire McNamara , Matthias Brugger , AngeloGioacchino Del Regno , Haibo Chen , Yogesh Gaur , Heiko Stuebner , Michal Simek , Miquel Raynal Subject: [PATCH 12/24] spi: rockchip-sfc: Support per spi-mem operation frequency switches Date: Fri, 25 Oct 2024 18:14:49 +0200 Message-ID: <20241025161501.485684-13-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025161501.485684-1-miquel.raynal@bootlin.com> References: <20241025161501.485684-1-miquel.raynal@bootlin.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: miquel.raynal@bootlin.com Every ->exec_op() call correctly configures the spi bus speed to the maximum allowed frequency for the memory using the constant spi default parameter. Since we can now have per-operation constraints, let's use the value that comes from the spi-mem operation structure instead. In case there is no specific limitation for this operation, the default spi device value will be given anyway. The per-operation frequency capability is thus advertised to the spi-mem core. Cc: Han Xu Cc: Haibo Chen Cc: Yogesh Gaur Signed-off-by: Miquel Raynal --- drivers/spi/spi-rockchip-sfc.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c index 0d7fadcd4ed3..1e0257b85f33 100644 --- a/drivers/spi/spi-rockchip-sfc.c +++ b/drivers/spi/spi-rockchip-sfc.c @@ -491,11 +491,11 @@ static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op u32 len = op->data.nbytes; int ret; - if (unlikely(mem->spi->max_speed_hz != sfc->frequency)) { - ret = clk_set_rate(sfc->clk, mem->spi->max_speed_hz); + if (unlikely(op->max_freq != sfc->frequency)) { + ret = clk_set_rate(sfc->clk, op->max_freq); if (ret) return ret; - sfc->frequency = mem->spi->max_speed_hz; + sfc->frequency = op->max_freq; dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n", sfc->frequency, clk_get_rate(sfc->clk)); } @@ -535,6 +535,10 @@ static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { .adjust_op_size = rockchip_sfc_adjust_op_size, }; +static const struct spi_controller_mem_caps rockchip_sfc_mem_caps = { + .per_op_freq = true, +}; + static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id) { struct rockchip_sfc *sfc = dev_id; @@ -567,6 +571,7 @@ static int rockchip_sfc_probe(struct platform_device *pdev) host->flags = SPI_CONTROLLER_HALF_DUPLEX; host->mem_ops = &rockchip_sfc_mem_ops; + host->mem_caps = &rockchip_sfc_mem_caps; host->dev.of_node = pdev->dev.of_node; host->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL; host->max_speed_hz = SFC_MAX_SPEED;