diff mbox series

[2/5] spi: zynqmp-gqspi: Reset device in probe

Message ID 20250116225521.2688224-3-sean.anderson@linux.dev (mailing list archive)
State New
Headers show
Series spi: zynqmp-gqspi: Improve error recovery by resetting | expand

Commit Message

Sean Anderson Jan. 16, 2025, 10:55 p.m. UTC 
Ensure we get a clean slate (without any bootloader settings) by
resetting the device before we initialize it.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---

 drivers/spi/spi-zynqmp-gqspi.c | 24 ++++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 549a6e0c9654..7d138f45b692 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -17,6 +17,7 @@ 
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/spi/spi.h>
 #include <linux/spinlock.h>
 #include <linux/workqueue.h>
@@ -171,6 +172,7 @@  struct qspi_platform_data {
  * @regs:		Virtual address of the QSPI controller registers
  * @refclk:		Pointer to the peripheral clock
  * @pclk:		Pointer to the APB clock
+ * @reset:		Pointer to reset controller
  * @irq:		IRQ number
  * @dev:		Pointer to struct device
  * @txbuf:		Pointer to the TX buffer
@@ -193,6 +195,7 @@  struct zynqmp_qspi {
 	void __iomem *regs;
 	struct clk *refclk;
 	struct clk *pclk;
+	struct reset_control *reset;
 	int irq;
 	struct device *dev;
 	const void *txbuf;
@@ -351,10 +354,17 @@  static void zynqmp_qspi_set_tapdelay(struct zynqmp_qspi *xqspi, u32 baudrateval)
  *	- Set clock polarity and
  *	- Enable the QSPI controller
  */
-static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
+static int zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
 {
 	u32 config_reg, baud_rate_val = 0;
 	ulong clk_rate;
+	int ret;
+
+	ret = reset_control_reset(xqspi->reset);
+	if (ret) {
+		dev_err(xqspi->dev, "Unable to reset: %pe\n", &ret);
+		return ret;
+	}
 
 	/* Select the GQSPI mode */
 	zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
@@ -436,6 +446,8 @@  static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
 
 	/* Enable the GQSPI */
 	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
+
+	return 0;
 }
 
 /**
@@ -1259,6 +1271,12 @@  static int zynqmp_qspi_probe(struct platform_device *pdev)
 	if (IS_ERR(xqspi->regs))
 		return PTR_ERR(xqspi->regs);
 
+	xqspi->reset =
+		devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+	if (IS_ERR(xqspi->reset))
+		return dev_err_probe(dev, PTR_ERR(xqspi->reset),
+				     "could not get reset\n");
+
 	xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
 	if (IS_ERR(xqspi->pclk))
 		return dev_err_probe(dev, PTR_ERR(xqspi->pclk),
@@ -1300,7 +1318,9 @@  static int zynqmp_qspi_probe(struct platform_device *pdev)
 	xqspi->speed_hz = ctlr->max_speed_hz;
 
 	/* QSPI controller initializations */
-	zynqmp_qspi_init_hw(xqspi);
+	ret = zynqmp_qspi_init_hw(xqspi);
+	if (ret)
+		goto clk_dis_all;
 
 	xqspi->irq = platform_get_irq(pdev, 0);
 	if (xqspi->irq < 0) {