| Message ID | 20250305200133.2511308-2-miquel.raynal@bootlin.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | spi: dt-bindings: cdns,qspi-nor: Improve description | expand |
On Wed, Mar 05, 2025 at 09:01:31PM +0100, Miquel Raynal wrote: > Despite being very common in commit logs, SPI NOR controllers simply do > not exist. At least, they are not as specific as the name implies. There > are SPI memory controllers which are indeed "specialized" and optimized > for handling "memories", but most of them are just generic and accept > almost any kind of opcode, address, dummy and data cycles, making them > as suitable for NANDs than NORs. > > Furthermore, this controller supports any kind of bus, from single to > octal NAND, so make it clear. > > Also add a comment to mention that the initial compatible naming is too > specific (but obviously kept for backward compatibility reasons). > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > --- > Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index b6bc71d19286..c4315b2e04f2 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Cadence Quad SPI controller +title: Cadence Quad/Octal SPI controller maintainers: - Vaishnav Achath <vaishnav.a@ti.com> @@ -76,6 +76,9 @@ properties: - ti,am654-ospi - ti,k2g-qspi - xlnx,versal-ospi-1.0 + # The compatible is qspi-nor for historical reasons but such + # controllers are meant to be used with flashes of all kinds, + # ie. also NAND flashes, not only NOR flashes. - const: cdns,qspi-nor - const: cdns,qspi-nor
Despite being very common in commit logs, SPI NOR controllers simply do not exist. At least, they are not as specific as the name implies. There are SPI memory controllers which are indeed "specialized" and optimized for handling "memories", but most of them are just generic and accept almost any kind of opcode, address, dummy and data cycles, making them as suitable for NANDs than NORs. Furthermore, this controller supports any kind of bus, from single to octal NAND, so make it clear. Also add a comment to mention that the initial compatible naming is too specific (but obviously kept for backward compatibility reasons). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)