@@ -2360,6 +2360,7 @@ static const struct qcom_nandc_props ipq806x_nandc_props = {
.supports_bam = false,
.use_codeword_fixup = true,
.dev_cmd_reg_start = 0x0,
+ .nandc_offset = 0x30000,
};
static const struct qcom_nandc_props ipq4019_nandc_props = {
@@ -2367,6 +2368,7 @@ static const struct qcom_nandc_props ipq4019_nandc_props = {
.supports_bam = true,
.nandc_part_of_qpic = true,
.dev_cmd_reg_start = 0x0,
+ .nandc_offset = 0x30000,
};
static const struct qcom_nandc_props ipq8074_nandc_props = {
@@ -2374,6 +2376,7 @@ static const struct qcom_nandc_props ipq8074_nandc_props = {
.supports_bam = true,
.nandc_part_of_qpic = true,
.dev_cmd_reg_start = 0x7000,
+ .nandc_offset = 0x30000,
};
static const struct qcom_nandc_props sdx55_nandc_props = {
@@ -2382,6 +2385,7 @@ static const struct qcom_nandc_props sdx55_nandc_props = {
.nandc_part_of_qpic = true,
.qpic_version2 = true,
.dev_cmd_reg_start = 0x7000,
+ .nandc_offset = 0x30000,
};
/*
@@ -200,7 +200,7 @@
#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
/* Returns the NAND register physical address */
-#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
+#define nandc_reg_phys(chip, offset) ((nandc)->props->nandc_offset + (offset))
/* Returns the dma address for reg read buffer */
#define reg_buf_dma_addr(chip, vaddr) \
@@ -458,6 +458,7 @@ struct qcom_nandc_props {
bool nandc_part_of_qpic;
bool qpic_version2;
bool use_codeword_fixup;
+ u32 nandc_offset;
};
void qcom_free_bam_transaction(struct qcom_nand_controller *nandc);
Currently we are configuring lower 24 bits of address in descriptor whereas QPIC design expects 18 bit register offset from QPIC base address to be configured in cmd descriptors. This is leading to a different address actually being used in HW, leading to wrong value read. the actual issue is that the NANDc base address is different from the QPIC base address. But the driver doesn't take it into account and just used the QPIC base as the NANDc base. This used to work as the NANDc IP only considers the lower 18 bits of the address passed by the driver to derive the register offset. Since the base address of QPIC used to contain all 0 for lower 18 bits (like 0x07980000), the driver ended up passing the actual register offset in it and NANDc worked properly. But on newer SoCs like SDX75, the QPIC base address doesn't contain all 0 for lower 18 bits (like 0x01C98000). So NANDc sees wrong offset as per the current logic The address should be passed to BAM 0x30000 + offset. In older targets the lower 18-bits are zero so that correct address being paased. But in newer targets the lower 18-bits are non-zero in QPIC base so that 0x300000 + offset giving the wrong value. SDX75 : QPIC_QPIC | 0x01C98000 (Lower 18 bits are non zero) SDX55 : QPIC_QPIC | 0x1B00000 (Lower 18 bits are zero) Same for older targets. Cc: stable@vger.kernel.org Fixes: 8d6b6d7e135e ("mtd: nand: qcom: support for command descriptor formation") Tested-by: Lakshmi Sowjanya D <quic_laksd@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> --- Change in [v3] * Updated commit message * Removed dev_cmd_reg_start = 0 , which was wrongely got added Change in [v2] * Updated commit message * Added Fixes tag * Added stable kernel tag * Renamed the variable from offset_from_qpic to nandc_offset Change in [v1] * Preliminary correction for the register address forwarded to BAM drivers/mtd/nand/raw/qcom_nandc.c | 4 ++++ include/linux/mtd/nand-qpic-common.h | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-)