| Message ID | 20250401134748.242846-1-miquel.raynal@bootlin.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 3cb2a2f7eebbb0752a834708e720a914e61841a1 |
| Headers | show |
| Series | [v2] spi: cadence-qspi: revert "Improve spi memory performance" | expand |
On Tue, 01 Apr 2025 15:47:47 +0200, Miquel Raynal wrote: > During the v6.14-rc cycles, there has been an issue with syscons which > prevented TI chipid controller to probe, itself preventing the only DMA > engine on AM62A with the memcpy capability to probe, which is needed for > the SPI controller to work in its most efficient configuration. > > The SPI controller on AM62A can be used in DAC and INDAC mode, which are > some kind of direct mapping vs. CPU-controlled SPI operations, > respectively. However, because of hardware constraints (some kind of > request line not being driven), INDAC mode cannot leverage DMA without > risking to underflow the SPI FIFO. This mode costs a lot of CPU > cycles. On the other side however, DAC mode can be used with and without > DMA support, but in practice, DMA transfers are way more efficient > because of the burst capabilities that the CPU does not have. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/1] spi: cadence-qspi: revert "Improve spi memory performance" commit: 3cb2a2f7eebbb0752a834708e720a914e61841a1 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 559fbdfbd9f7..c90462783b3f 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -2073,7 +2073,7 @@ static const struct cqspi_driver_platdata k2g_qspi = { static const struct cqspi_driver_platdata am654_ospi = { .hwcaps_mask = CQSPI_SUPPORTS_OCTAL | CQSPI_SUPPORTS_QUAD, - .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NEEDS_WR_DELAY, + .quirks = CQSPI_NEEDS_WR_DELAY, }; static const struct cqspi_driver_platdata intel_lgm_qspi = {
During the v6.14-rc cycles, there has been an issue with syscons which prevented TI chipid controller to probe, itself preventing the only DMA engine on AM62A with the memcpy capability to probe, which is needed for the SPI controller to work in its most efficient configuration. The SPI controller on AM62A can be used in DAC and INDAC mode, which are some kind of direct mapping vs. CPU-controlled SPI operations, respectively. However, because of hardware constraints (some kind of request line not being driven), INDAC mode cannot leverage DMA without risking to underflow the SPI FIFO. This mode costs a lot of CPU cycles. On the other side however, DAC mode can be used with and without DMA support, but in practice, DMA transfers are way more efficient because of the burst capabilities that the CPU does not have. As a result, in terms of read throughput, using a Winbond chip in 1-8-8 SDR mode, we get: - 3.5MiB/s in DAC mode without DMA - 9.0MiB/s in INDAC mode (CPU more busy) - a fluctuating 9 to 12MiB/s in DAC mode with DMA (a constant 14.5MiB/s without CPUfreq) The reason for the patch that is being reverted is that because of the syscon issue, we were using a very un-efficient DAC configuration (no DMA), but since: commit 5728c92ae112 ("mfd: syscon: Restore device_node_to_regmap() for non-syscon nodes") the probing of the DMA controller has been fixed, and the performances are back to normal, so we can safely revert this commit. This is a revert of: commit cce2200dacd6 ("spi: cadence-qspi: Improve spi memory performance") Suggested-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- Changes in v2: - Fix the commit hash. - Fix the commit title. - Fix the wording around the commit being reverted. --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)