From patchwork Thu Jul 16 15:27:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyrille Pitchen X-Patchwork-Id: 6808191 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 17038C05AC for ; Thu, 16 Jul 2015 15:29:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 44204205B8 for ; Thu, 16 Jul 2015 15:29:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4CCB320576 for ; Thu, 16 Jul 2015 15:29:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755155AbbGPP1u (ORCPT ); Thu, 16 Jul 2015 11:27:50 -0400 Received: from eusmtp01.atmel.com ([212.144.249.243]:20589 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754545AbbGPP1t (ORCPT ); Thu, 16 Jul 2015 11:27:49 -0400 Received: from tenerife.corp.atmel.com (10.161.101.13) by eusmtp01.atmel.com (10.161.101.31) with Microsoft SMTP Server id 14.3.235.1; Thu, 16 Jul 2015 17:27:43 +0200 From: Cyrille Pitchen To: , , , , , , , , , , CC: , , , , , , , , , Cyrille Pitchen Subject: [PATCH 4/7] Documentation: mtd: add a DT property to set the latency code of Spansion memory Date: Thu, 16 Jul 2015 17:27:51 +0200 Message-ID: <398ca9f17bda638e05e97f258fb4e6d27ac828db.1437059658.git.cyrille.pitchen@atmel.com> X-Mailer: git-send-email 1.8.2.2 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Both the SPI controller and the NOR flash memory need to agree on the number of dummy cycles to use for Fast Read commands. For Spansion memories, this number of dummy cycles is not given directly but through a so called "latency code". The latency code can be found into the memory datasheet and depends on the SPI clock frequency, the Fast Read op code and the Single/Dual Data Rate mode. Signed-off-by: Cyrille Pitchen --- .../devicetree/bindings/mtd/spansion-nor.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/spansion-nor.txt diff --git a/Documentation/devicetree/bindings/mtd/spansion-nor.txt b/Documentation/devicetree/bindings/mtd/spansion-nor.txt new file mode 100644 index 000000000000..a55c62db0e6f --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/spansion-nor.txt @@ -0,0 +1,22 @@ +* Spansion NOR flash + +Optional properties: +- spansion,latency-code : Only used when the "m25p,num-dummy-cycles" property is + set. The Spansion latency code tells the NOR flash + memory the number of dummy cycles to expect for each + Fast Read command. The value to be used is provided by + tables in the memory datasheet and depends on the SPI + clock frequency and on the Single/Dual Data Rate mode. + Then the value of "m25p,num-dummy-cycles" property + should match the (Fast) Read command to be used for + the chosen latency code. + +Example: + + m25p80@0 { + compatible = "spansion,s25fl512s"; + reg = <0>; + spi-max-frequency = <104000000>; + m25p,num-dummy-cycles = <8>; + spansion,latency-code = <2>; + };