@@ -479,14 +479,13 @@ static int xilinx_spi_probe(struct platform_device *dev)
#ifdef CONFIG_OF
if (dev->dev.of_node) {
- const __be32 *prop;
- int len;
-
/* number of slave select bits is required */
- prop = of_get_property(dev->dev.of_node, "xlnx,num-ss-bits",
- &len);
- if (prop && len >= sizeof(*prop))
- num_cs = __be32_to_cpup(prop);
+ of_property_read_u32(dev->dev.of_node, "xlnx,num-ss-bits",
+ &num_cs);
+
+ /* override default number of bits per word */
+ of_property_read_u32(dev->dev.of_node, "xlnx,num-transfer-bits",
+ &bits_per_word);
}
#endif
new file mode 100644
@@ -0,0 +1,32 @@
+Xilinx SPI controller:
+
+Required properties:
+- compatible : Must be "xlnx,axi-1.02.a" or "xlnx,xps-spi-2.00.a"
+- interrupt-parent : reference to parent interrupt controller
+- interrupts : SPI controller interrupt
+- reg : SPI register location and length
+
+Optional properties:
+- xlnx,num-ss-bits : # of slave select bits
+- xlnx,num-transfer_bits : # of data transfer bits (defaults to 8)
+- xlnx,... : not considered by kernel module
+- #address-cells = <1> : if child nodes are defined
+- #size-cells = <0> : if child nodes are defined
+- Child nodes conforming to SPI bus binding
+
+Example with 3 slave select bits and 32 bit transfer size:
+
+ axi_spi_0: spi@40a00000 {
+ compatible = "xlnx,axi-spi-1.02.a", "xlnx,xps-spi-2.00.a";
+ interrupt-parent = <&axi_intc_0>;
+ interrupts = < 2 2 >;
+ reg = < 0x40a00000 0x10000 >;
+ xlnx,family = "spartan6";
+ xlnx,fifo-exist = <0x1>;
+ xlnx,instance = "axi_spi_0";
+ xlnx,num-ss-bits = <0x3>;
+ xlnx,num-transfer-bits = <0x20>;
+ xlnx,sck-ratio = <0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ } ;