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[2003:62:5f43:9500:6565:4488:ad4:60db]) by smtp.googlemail.com with ESMTPSA id o5sm6037801wmg.16.2016.09.07.13.55.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Sep 2016 13:55:47 -0700 (PDT) From: Heiner Kallweit Subject: [PATCH v3 10/15] spi: fsl-espi: improve the ISR frame To: Mark Brown References: Cc: "linux-spi@vger.kernel.org" Message-ID: <7733dbde-1950-d6e3-6d71-975b25d6ded1@gmail.com> Date: Wed, 7 Sep 2016 22:53:23 +0200 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Improve the ISR frame: - move resetting the event bits to the ISR frame - change type of parameter irq to int - make sure that the event bits match at least one bit in the interrupt mask register Signed-off-by: Heiner Kallweit --- v2: - rebased v3: - new numbering --- drivers/spi/spi-fsl-espi.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c index 190ca5c..534dc14 100644 --- a/drivers/spi/spi-fsl-espi.c +++ b/drivers/spi/spi-fsl-espi.c @@ -451,17 +451,11 @@ static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) ®_base->event)) & SPIE_NF), 1000, 0); if (!ret) { dev_err(mspi->dev, "tired waiting for SPIE_NF\n"); - - /* Clear the SPIE bits */ - mpc8xxx_spi_write_reg(®_base->event, events); complete(&mspi->done); return; } } - /* Clear the events */ - mpc8xxx_spi_write_reg(®_base->event, events); - mspi->count -= 1; if (mspi->count) { u32 word = mspi->get_tx(mspi); @@ -472,23 +466,26 @@ static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) } } -static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) +static irqreturn_t fsl_espi_irq(int irq, void *context_data) { struct mpc8xxx_spi *mspi = context_data; struct fsl_espi_reg *reg_base = mspi->reg_base; - irqreturn_t ret = IRQ_NONE; - u32 events; + u32 mask, events; - /* Get interrupt events(tx/rx) */ + /* Get interrupt mask and events and check that irq belongs to us */ + mask = mpc8xxx_spi_read_reg(®_base->mask); events = mpc8xxx_spi_read_reg(®_base->event); - if (events) - ret = IRQ_HANDLED; + if (!(mask & events)) + return IRQ_NONE; dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); fsl_espi_cpu_irq(mspi, events); - return ret; + /* Clear the events */ + mpc8xxx_spi_write_reg(®_base->event, events); + + return IRQ_HANDLED; } #ifdef CONFIG_PM