From patchwork Fri Sep 25 16:55:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 7266681 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9BA86BEEC1 for ; Fri, 25 Sep 2015 16:56:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A3AEC20942 for ; Fri, 25 Sep 2015 16:56:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9CB47208C2 for ; Fri, 25 Sep 2015 16:56:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932548AbbIYQ4V (ORCPT ); Fri, 25 Sep 2015 12:56:21 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:49689 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932498AbbIYQ4U (ORCPT ); Fri, 25 Sep 2015 12:56:20 -0400 Received: from [70.35.39.2] (helo=finisterre) by mezzanine.sirena.org.uk with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1ZfWIF-0004xs-Dh; Fri, 25 Sep 2015 16:56:19 +0000 Received: from broonie by finisterre with local (Exim 4.86) (envelope-from ) id 1ZfWHg-0001Y4-NQ; Fri, 25 Sep 2015 09:55:44 -0700 From: Mark Brown To: Jarkko Nikula , Mark Brown Cc: linux-spi@vger.kernel.org In-Reply-To: <1443166038-31658-1-git-send-email-jarkko.nikula@linux.intel.com> Message-Id: Date: Fri, 25 Sep 2015 09:55:44 -0700 X-SA-Exim-Connect-IP: 70.35.39.2 X-SA-Exim-Mail-From: broonie@sirena.org.uk X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Subject: Applied "spi: pxa2xx: Set the max_speed_hz of the master" to the spi tree X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch spi: pxa2xx: Set the max_speed_hz of the master has been applied to the spi tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark From 0eca7cf2696506006463b9d67bb6110c82d3e064 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Fri, 25 Sep 2015 10:27:17 +0300 Subject: [PATCH] spi: pxa2xx: Set the max_speed_hz of the master Carry input clock of the controller in max_speed_hz of struct spi_master instead of in own driver data. They mean the same thing and more over now the max_speed_hz is not even set here. As an added bonus this allows SPI core to validate that transfer speed is not beyond the maximum input clock. This is not a problem in spi-pxa2xx as the driver doesn't use transfer speed parameter directly but via input clock divider calculation which will top at divide by one. However it's better to validate speed before passing it here. Signed-off-by: Jarkko Nikula Signed-off-by: Mark Brown --- drivers/spi/spi-pxa2xx.c | 12 ++++++------ drivers/spi/spi-pxa2xx.h | 3 --- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index a25bc1d..0e075db 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -802,7 +802,7 @@ static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) { - unsigned long ssp_clk = drv_data->max_clk_rate; + unsigned long ssp_clk = drv_data->master->max_speed_hz; const struct ssp_device *ssp = drv_data->ssp; rate = min_t(int, ssp_clk, rate); @@ -1217,13 +1217,13 @@ static int setup(struct spi_device *spi) /* NOTE: PXA25x_SSP _could_ use external clocking ... */ cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, spi->bits_per_word); if (!pxa25x_ssp_comp(drv_data)) - dev_dbg(&spi->dev, "%ld Hz actual, %s\n", - drv_data->max_clk_rate + dev_dbg(&spi->dev, "%u Hz actual, %s\n", + drv_data->master->max_speed_hz / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), chip->enable_dma ? "DMA" : "PIO"); else - dev_dbg(&spi->dev, "%ld Hz actual, %s\n", - drv_data->max_clk_rate / 2 + dev_dbg(&spi->dev, "%u Hz actual, %s\n", + drv_data->master->max_speed_hz / 2 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), chip->enable_dma ? "DMA" : "PIO"); @@ -1473,7 +1473,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) /* Enable SOC clock */ clk_prepare_enable(ssp->clk); - drv_data->max_clk_rate = clk_get_rate(ssp->clk); + master->max_speed_hz = clk_get_rate(ssp->clk); /* Load default SSP configuration */ pxa2xx_spi_write(drv_data, SSCR0, 0); diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h index b91bda2..fd7a7bc 100644 --- a/drivers/spi/spi-pxa2xx.h +++ b/drivers/spi/spi-pxa2xx.h @@ -46,9 +46,6 @@ struct driver_data { u32 clear_sr; u32 mask_sr; - /* Maximun clock rate */ - unsigned long max_clk_rate; - /* Message Transfer pump */ struct tasklet_struct pump_transfers;