From patchwork Mon Jul 4 14:17:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 9212737 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 59E4660467 for ; Mon, 4 Jul 2016 14:17:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4C8F928715 for ; Mon, 4 Jul 2016 14:17:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 418F42871B; Mon, 4 Jul 2016 14:17:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE5B428715 for ; Mon, 4 Jul 2016 14:17:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753904AbcGDORr (ORCPT ); Mon, 4 Jul 2016 10:17:47 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:41278 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753686AbcGDORr (ORCPT ); Mon, 4 Jul 2016 10:17:47 -0400 Received: from [137.158.22.87] (helo=finisterre) by mezzanine.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.84_2) (envelope-from ) id 1bK4gy-0000nA-C1; Mon, 04 Jul 2016 14:17:45 +0000 Received: from broonie by finisterre with local (Exim 4.87) (envelope-from ) id 1bK4gi-0006JF-9B; Mon, 04 Jul 2016 16:17:28 +0200 From: Mark Brown To: Andy Shevchenko Cc: Mark Brown , Robert Jarzmik , linux-spi@vger.kernel.org, Mark Brown , Jarkko Nikula In-Reply-To: <1467625467-103785-3-git-send-email-andriy.shevchenko@linux.intel.com> Message-Id: Date: Mon, 04 Jul 2016 16:17:28 +0200 X-SA-Exim-Connect-IP: 137.158.22.87 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Applied "spi: pxa2xx-pci: Enable SPI on Intel Merrifield" to the spi tree X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch spi: pxa2xx-pci: Enable SPI on Intel Merrifield has been applied to the spi tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark From 4f4709109ef7e1248b5515c68df4b9c5ad39fbdf Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 4 Jul 2016 12:44:25 +0300 Subject: [PATCH] spi: pxa2xx-pci: Enable SPI on Intel Merrifield The SPI controllers used on Intel Merrifield are PXA2XX compatible. This patch enables them. Signed-off-by: Andy Shevchenko Signed-off-by: Mark Brown --- drivers/spi/spi-pxa2xx-pci.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c index 8d58598c325d..b025eaf14f0f 100644 --- a/drivers/spi/spi-pxa2xx-pci.c +++ b/drivers/spi/spi-pxa2xx-pci.c @@ -15,6 +15,7 @@ enum { PORT_CE4100, PORT_BYT, + PORT_MRFLD, PORT_BSW0, PORT_BSW1, PORT_BSW2, @@ -89,6 +90,27 @@ static int lpss_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c) return 0; } +static int mrfld_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c) +{ + switch (PCI_FUNC(dev->devfn)) { + case 0: + c->port_id = 3; + c->num_chipselect = 1; + break; + case 1: + c->port_id = 5; + c->num_chipselect = 4; + break; + case 2: + c->port_id = 6; + c->num_chipselect = 1; + break; + default: + return -ENODEV; + } + return 0; +} + static struct pxa_spi_info spi_info_configs[] = { [PORT_CE4100] = { .type = PXA25x_SSP, @@ -124,6 +146,11 @@ static struct pxa_spi_info spi_info_configs[] = { .tx_param = &bsw2_tx_param, .rx_param = &bsw2_rx_param, }, + [PORT_MRFLD] = { + .type = PXA27x_SSP, + .max_clk_rate = 25000000, + .setup = mrfld_spi_setup, + }, [PORT_QUARK_X1000] = { .type = QUARK_X1000_SSP, .port_id = -1, @@ -222,6 +249,7 @@ static const struct pci_device_id pxa2xx_spi_pci_devices[] = { { PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 }, { PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 }, { PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT }, + { PCI_VDEVICE(INTEL, 0x1194), PORT_MRFLD }, { PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 }, { PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 }, { PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 },