From patchwork Fri Nov 11 16:01:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 9423205 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 649FC60233 for ; Fri, 11 Nov 2016 16:02:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 60C5E29B9C for ; Fri, 11 Nov 2016 16:02:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5588F29BA0; Fri, 11 Nov 2016 16:02:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF82629B9C for ; Fri, 11 Nov 2016 16:02:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755811AbcKKQB5 (ORCPT ); Fri, 11 Nov 2016 11:01:57 -0500 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:39954 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756128AbcKKQB4 (ORCPT ); Fri, 11 Nov 2016 11:01:56 -0500 Received: from 94.197.121.150.threembb.co.uk ([94.197.121.150] helo=finisterre) by mezzanine.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.84_2) (envelope-from ) id 1c5EGu-0005jZ-4D; Fri, 11 Nov 2016 16:01:46 +0000 Received: from broonie by finisterre with local (Exim 4.87) (envelope-from ) id 1c5EGk-0003pI-Mc; Fri, 11 Nov 2016 16:01:34 +0000 From: Mark Brown To: Heiner Kallweit Cc: Mark Brown , Mark Brown , "linux-spi@vger.kernel.org" , linux-spi@vger.kernel.org In-Reply-To: <0e96f53c-5e83-77bd-a57a-2e576ca20019@gmail.com> Message-Id: Date: Fri, 11 Nov 2016 16:01:34 +0000 X-SA-Exim-Connect-IP: 94.197.121.150 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Applied "spi: fsl-espi: add support for ESPI RXSKIP mode" to the spi tree X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: No (on mezzanine.sirena.org.uk); Unknown failure Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch spi: fsl-espi: add support for ESPI RXSKIP mode has been applied to the spi tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark From aca75157d9beb7b171a178446ecdb4d047b9f934 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Wed, 9 Nov 2016 22:58:01 +0100 Subject: [PATCH] spi: fsl-espi: add support for ESPI RXSKIP mode This patch adds support for ESPI RXSKIP mode. This mode is optimized for flash reads: - sends a number of bytes and then reads a number of bytes - shifts out zeros automatically when reading Supporting RXSKIP mode is a prerequisite for supporting dual output read mode. Signed-off-by: Heiner Kallweit Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-espi.c | 51 ++++++++++++++++++++++++++++++++++++++++++---- drivers/spi/spi-fsl-lib.h | 1 + 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c index edb524f831a3..9ccbfbc75933 100644 --- a/drivers/spi/spi-fsl-espi.c +++ b/drivers/spi/spi-fsl-espi.c @@ -150,7 +150,8 @@ static void fsl_espi_copy_to_buf(struct spi_message *m, list_for_each_entry(t, &m->transfers, transfer_list) { if (t->tx_buf) fsl_espi_memcpy_swab(buf, t->tx_buf, m, t); - else + /* In RXSKIP mode controller shifts out zeros internally */ + else if (!mspi->rxskip) memset(buf, 0, t->len); buf += t->len; } @@ -203,6 +204,37 @@ static int fsl_espi_check_message(struct spi_message *m) return 0; } +static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m) +{ + struct spi_transfer *t; + unsigned int i = 0, rxskip = 0; + + /* + * prerequisites for ESPI rxskip mode: + * - message has two transfers + * - first transfer is a write and second is a read + * + * In addition the current low-level transfer mechanism requires + * that the rxskip bytes fit into the TX FIFO. Else the transfer + * would hang because after the first FSL_ESPI_FIFO_SIZE bytes + * the TX FIFO isn't re-filled. + */ + list_for_each_entry(t, &m->transfers, transfer_list) { + if (i == 0) { + if (!t->tx_buf || t->rx_buf || + t->len > FSL_ESPI_FIFO_SIZE) + return 0; + rxskip = t->len; + } else if (i == 1) { + if (t->tx_buf || !t->rx_buf) + return 0; + } + i++; + } + + return i == 2 ? rxskip : 0; +} + static void fsl_espi_fill_tx_fifo(struct mpc8xxx_spi *mspi, u32 events) { u32 tx_fifo_avail; @@ -281,7 +313,7 @@ static void fsl_espi_setup_transfer(struct spi_device *spi, static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) { struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); - u32 mask; + u32 mask, spcom; int ret; mpc8xxx_spi->rx_len = t->len; @@ -293,8 +325,18 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) reinit_completion(&mpc8xxx_spi->done); /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ - fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, - (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1))); + spcom = SPCOM_CS(spi->chip_select); + spcom |= SPCOM_TRANLEN(t->len - 1); + + /* configure RXSKIP mode */ + if (mpc8xxx_spi->rxskip) { + spcom |= SPCOM_RXSKIP(mpc8xxx_spi->rxskip); + mpc8xxx_spi->tx_len = mpc8xxx_spi->rxskip; + mpc8xxx_spi->rx_len = t->len - mpc8xxx_spi->rxskip; + mpc8xxx_spi->rx = t->rx_buf + mpc8xxx_spi->rxskip; + } + + fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, spcom); /* enable interrupts */ mask = SPIM_DON; @@ -326,6 +368,7 @@ static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) struct spi_device *spi = m->spi; int ret; + mspi->rxskip = fsl_espi_check_rxskip_mode(m); fsl_espi_copy_to_buf(m, mspi); fsl_espi_setup_transfer(spi, trans); diff --git a/drivers/spi/spi-fsl-lib.h b/drivers/spi/spi-fsl-lib.h index 35a7a1730d0c..3951322265d4 100644 --- a/drivers/spi/spi-fsl-lib.h +++ b/drivers/spi/spi-fsl-lib.h @@ -31,6 +31,7 @@ struct mpc8xxx_spi { #if IS_ENABLED(CONFIG_SPI_FSL_ESPI) unsigned int rx_len; unsigned int tx_len; + unsigned int rxskip; u8 *local_buf; spinlock_t lock; #endif