From patchwork Thu Nov 8 07:06:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lukas Wunner X-Patchwork-Id: 10673615 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1EFD31751 for ; Thu, 8 Nov 2018 07:17:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0796A2C36C for ; Thu, 8 Nov 2018 07:17:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EDCC82C9B9; Thu, 8 Nov 2018 07:17:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B3B12C36C for ; Thu, 8 Nov 2018 07:17:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725724AbeKHQv1 (ORCPT ); Thu, 8 Nov 2018 11:51:27 -0500 Received: from mailout3.hostsharing.net ([176.9.242.54]:55269 "EHLO mailout3.hostsharing.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726663AbeKHQv0 (ORCPT ); Thu, 8 Nov 2018 11:51:26 -0500 Received: from h08.hostsharing.net (h08.hostsharing.net [83.223.95.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "*.hostsharing.net", Issuer "COMODO RSA Domain Validation Secure Server CA" (not verified)) by mailout3.hostsharing.net (Postfix) with ESMTPS id 9361F101E6B2D; Thu, 8 Nov 2018 08:17:17 +0100 (CET) Received: from localhost (unknown [89.246.108.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by h08.hostsharing.net (Postfix) with ESMTPSA id 25CCE603E05D; Thu, 8 Nov 2018 08:17:17 +0100 (CET) X-Mailbox-Line: From a24869503ed4e867b11c66c8615a4d5cddb3b2b5 Mon Sep 17 00:00:00 2001 Message-Id: In-Reply-To: References: From: Lukas Wunner Date: Thu, 8 Nov 2018 08:06:10 +0100 Subject: [PATCH 4/7] spi: bcm2835: Drop unused code for native Chip Select MIME-Version: 1.0 To: Mark Brown , Eric Anholt , Stefan Wahren Cc: Mathias Duckeck , Frank Pavlic , Martin Sperl , Noralf Tronnes , linux-spi@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit a30a555d7435 ("spi: bcm2835: transform native-cs to gpio-cs on first spi_setup") disabled the use of hardware-controlled native Chip Select in favour of software-controlled GPIO Chip Select but left code to support the former untouched. Remove it to simplify the driver and ease the addition of new features and further optimizations. Signed-off-by: Lukas Wunner Cc: Mathias Duckeck Cc: Frank Pavlic Cc: Martin Sperl Cc: Noralf Trønnes --- drivers/spi/spi-bcm2835.c | 96 ++++++--------------------------------- 1 file changed, 13 insertions(+), 83 deletions(-) diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c index 774161bbcb2e..b2febd8e806e 100644 --- a/drivers/spi/spi-bcm2835.c +++ b/drivers/spi/spi-bcm2835.c @@ -172,28 +172,16 @@ static int bcm2835_spi_transfer_one_irq(struct spi_master *master, { struct bcm2835_spi *bs = spi_master_get_devdata(master); - /* fill in fifo if we have gpio-cs - * note that there have been rare events where the native-CS - * flapped for <1us which may change the behaviour - * with gpio-cs this does not happen, so it is implemented - * only for this case - */ - if (gpio_is_valid(spi->cs_gpio)) { - /* enable HW block, but without interrupts enabled - * this would triggern an immediate interrupt - */ - bcm2835_wr(bs, BCM2835_SPI_CS, - cs | BCM2835_SPI_CS_TA); - /* fill in tx fifo as much as possible */ - bcm2835_wr_fifo(bs); - } - /* - * Enable the HW block. This will immediately trigger a DONE (TX - * empty) interrupt, upon which we will fill the TX FIFO with the - * first TX bytes. Pre-filling the TX FIFO here to avoid the - * interrupt doesn't work:-( + * Enable HW block, but with interrupts still disabled. + * Otherwise the empty TX FIFO would immediately trigger an interrupt. */ + bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); + + /* fill TX FIFO as much as possible */ + bcm2835_wr_fifo(bs); + + /* enable interrupts */ cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; bcm2835_wr(bs, BCM2835_SPI_CS, cs); @@ -356,10 +344,6 @@ static bool bcm2835_spi_can_dma(struct spi_master *master, struct spi_device *spi, struct spi_transfer *tfr) { - /* only run for gpio_cs */ - if (!gpio_is_valid(spi->cs_gpio)) - return false; - /* we start DMA efforts only on bigger transfers */ if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) return false; @@ -559,12 +543,12 @@ static int bcm2835_spi_transfer_one(struct spi_master *master, else cs &= ~BCM2835_SPI_CS_REN; - /* for gpio_cs set dummy CS so that no HW-CS get changed - * we can not run this in bcm2835_spi_set_cs, as it does - * not get called for cs_gpio cases, so we need to do it here + /* + * The driver always uses software-controlled GPIO Chip Select. + * Set the hardware-controlled native Chip Select to an invalid + * value to prevent it from interfering. */ - if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS)) - cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; + cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; /* set transmit buffers and length */ bs->tx_buf = tfr->tx_buf; @@ -624,59 +608,6 @@ static void bcm2835_spi_handle_err(struct spi_master *master, bcm2835_spi_reset_hw(master); } -static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level) -{ - /* - * we can assume that we are "native" as per spi_set_cs - * calling us ONLY when cs_gpio is not set - * we can also assume that we are CS < 3 as per bcm2835_spi_setup - * we would not get called because of error handling there. - * the level passed is the electrical level not enabled/disabled - * so it has to get translated back to enable/disable - * see spi_set_cs in spi.c for the implementation - */ - - struct spi_master *master = spi->master; - struct bcm2835_spi *bs = spi_master_get_devdata(master); - u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); - bool enable; - - /* calculate the enable flag from the passed gpio_level */ - enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level; - - /* set flags for "reverse" polarity in the registers */ - if (spi->mode & SPI_CS_HIGH) { - /* set the correct CS-bits */ - cs |= BCM2835_SPI_CS_CSPOL; - cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select; - } else { - /* clean the CS-bits */ - cs &= ~BCM2835_SPI_CS_CSPOL; - cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select); - } - - /* select the correct chip_select depending on disabled/enabled */ - if (enable) { - /* set cs correctly */ - if (spi->mode & SPI_NO_CS) { - /* use the "undefined" chip-select */ - cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; - } else { - /* set the chip select */ - cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01); - cs |= spi->chip_select; - } - } else { - /* disable CSPOL which puts HW-CS into deselected state */ - cs &= ~BCM2835_SPI_CS_CSPOL; - /* use the "undefined" chip-select as precaution */ - cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; - } - - /* finally set the calculated flags in SPI_CS */ - bcm2835_wr(bs, BCM2835_SPI_CS, cs); -} - static int chip_match_name(struct gpio_chip *chip, void *data) { return !strcmp(chip->label, data); @@ -748,7 +679,6 @@ static int bcm2835_spi_probe(struct platform_device *pdev) master->bits_per_word_mask = SPI_BPW_MASK(8); master->num_chipselect = 3; master->setup = bcm2835_spi_setup; - master->set_cs = bcm2835_spi_set_cs; master->transfer_one = bcm2835_spi_transfer_one; master->handle_err = bcm2835_spi_handle_err; master->prepare_message = bcm2835_spi_prepare_message;