From patchwork Mon Jul 22 21:39:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 11053503 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4D8D1138D for ; Mon, 22 Jul 2019 21:41:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3F08E2847E for ; Mon, 22 Jul 2019 21:41:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 30DB3284DB; Mon, 22 Jul 2019 21:41:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B6DA42847E for ; Mon, 22 Jul 2019 21:41:32 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hpg2T-0002Pt-5z; Mon, 22 Jul 2019 21:40:09 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hpg2R-0002MS-Km for xen-devel@lists.xenproject.org; Mon, 22 Jul 2019 21:40:07 +0000 X-Inumbo-ID: 451f2d58-acc9-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 451f2d58-acc9-11e9-8980-bc764e045a96; Mon, 22 Jul 2019 21:40:06 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B53C2344; Mon, 22 Jul 2019 14:40:05 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 07EB33F71F; Mon, 22 Jul 2019 14:40:04 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 22 Jul 2019 22:39:23 +0100 Message-Id: <20190722213958.5761-1-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 Subject: [Xen-devel] [PATCH v2 00/35] xen/arm: Rework head.S to make it more compliant with the Arm Arm X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , Stefano Stabellini , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Hi all, This is part of the boot/memory rework for Xen on Arm, but not sent as MM-PARTx as this is focusing on the boot code. Similar to the memory code, the boot code is not following the Arm Arm and could lead to memory corruption/TLB conflict abort. I am not aware of any platforms where Xen fails to boot, yet it should be fixed sooner rather than later. While making the code more compliant, I have also took the opportunity to simplify the boot and also add more documentation. After this series, the boot CPU and secondary CPUs path is mostly compliant with the Arm Arm. The only non-compliant places I am aware of are: 1) create_page_tables: Some rework is necessary to update the page-tables safely without the MMU on. 2) The switches between boot and runtime page-tables (for both boot CPU and secondary CPUs) are not safe. 3) The 1:1 mapping should only use page granularity mapping to avoid mapping memory that should not be accessed All will be addressed in follow-up series. The boot code would also benefits another proof read for missing isb()/dsb(). The arm32 code has been aded in this version but so far lightly tested. For convenience I provided a branch based on staging: git://xenbits.xen.org/people/julieng/xen-unstable.git branch boot/v2 Cheers, Julien Grall (35): xen/arm64: macros: Introduce an assembly macro to alias x30 xen/arm64: head: Mark the end of subroutines with ENDPROC xen/arm64: head: Don't clobber x30/lr in the macro PRINT xen/arm64: head: Rework UART initialization on boot CPU xen/arm64: head: Introduce print_reg xen/arm64: head: Introduce distinct paths for the boot CPU and secondary CPUs xen/arm64: head: Rework and document check_cpu_mode() xen/arm64: head: Rework and document zero_bss() xen/arm64: head: Improve coding style and document cpu_init() xen/arm64: head: Improve coding style and document create_pages_tables() xen/arm64: head: Document enable_mmu() xen/arm64: head: Move assembly switch to the runtime PT in secondary CPUs path xen/arm64: head: Don't setup the fixmap on secondary CPUs xen/arm64: head: Remove 1:1 mapping as soon as it is not used xen/arm64: head: Rework and document setup_fixmap() xen/arm64: head: Rework and document launch() xen/arm64: head: Setup TTBR_EL2 in enable_mmu() and add missing isb xen/arm64: head: Introduce a macro to get a PC-relative address of a symbol xen/arm32: head: Add a macro to move an immediate constant into a 32-bit register xen/arm32: head: Mark the end of subroutines with ENDPROC xen/arm32: head: Don't clobber r14/lr in the macro PRINT xen/arm32: head: Rework UART initialization on boot CPU xen/arm32: head: Introduce print_reg xen/arm32: head: Introduce distinct paths for the boot CPU and secondary CPUs xen/arm32: head: Rework and document check_cpu_mode() xen/arm32: head: Rework and document zero_bss() xen/arm32: head: Document create_pages_tables() xen/arm32: head: Document enable_mmu() xen/arm32: head: Move assembly switch to the runtime PT in secondary CPUs path xen/arm32: head: Don't setup the fixmap on secondary CPUs xen/arm32: head: Remove 1:1 mapping as soon as it is not used xen/arm32: head: Rework and document setup_fixmap() xen/arm32: head: Rework and document launch() xen/arm32: head: Setup HTTBR in enable_mmu() and add missing isb xen/arm: Zero BSS after the MMU and D-cache is turned on xen/arch/arm/arm32/head.S | 393 +++++++++++++++++++++++---------- xen/arch/arm/arm64/entry.S | 5 - xen/arch/arm/arm64/head.S | 432 +++++++++++++++++++++++++++---------- xen/arch/arm/mm.c | 23 +- xen/include/asm-arm/arm64/macros.h | 5 + 5 files changed, 619 insertions(+), 239 deletions(-)