[0/2] x86/pvshim: improve tlb flush performance

Message

Roger Pau Monné Nov. 25, 2019, 5:22 p.m. UTC

Hello,

Enabling PGE in CR4 causes a huge performance penalty when running the
shim on AMD hardware, this patch series avoids enabling PGE when in
shim mode, and makes a small adjustment in do_tlb_flush to perform a
flush by writing to CR3 if PGE is not enabled.

Roger Pau Monne (2):
  x86/tlbflush: do not toggle the PGE CR4 bit unless necessary
  x86/pvshim: do not enable global pages in shim mode

 xen/arch/x86/flushtlb.c  | 9 +++++----
 xen/arch/x86/pv/domain.c | 3 ++-
 2 files changed, 7 insertions(+), 5 deletions(-)