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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 00/12] Arm: Enable GICv3 for AArch32 (v8R) Date: Mon, 31 Oct 2022 15:13:14 +0000 Message-ID: <20221031151326.22634-1-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT013:EE_|DM4PR12MB5964:EE_ X-MS-Office365-Filtering-Correlation-Id: e78dc95d-ad04-436c-38c5-08dabb52825f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6yz0vOqDq+kKopEOAU7ZV2KULxnX7D3ludZhoq39TMBYG2jTdfE/NbTCw1fQUAHtf4vSNyVJBOc/4Vi20w/hxE74oBQ/iyukG00PDHKtvgmQCjhTydNaoEMqFGXOl1LRp/vpft30xwbINZ3fnqIdZiZnDx607ru2MQVo0kKWGPOEmTi7NOENKt+fxIMMM61nQB4P53FnEQmMbXzVtWqiiGG5WUP1ctK3Wl39TNXZuAL3KDF6MURLFo/QCuwSHNJP1/sBvqpROHk9ybQg7AIA2cR3UEX1yM5qEXYZq/bK6neNCO4eTEVe+7XGjroGIaCjk8o0YpT+CDLJsdXYiw3sgkkzC1UyM/fC/Puf29+SJyUxQLujm5lI8GNEiMxA6DnWvOagi2oRG7zlCFrsm0y/64AGGz2FlXt3JYCHVpLBeE8Pg49DicnrgcxO8/DMVvxm/XQqNOEgJLr26hF6ITb10pu75XlMZ7OIFV76+8Ocumb76taOBzyBjX2pqWzg7t9ktIuHuZdJx0z55LSiM0trDRC8ifXhhg/p69xTuv2nx5It9O0ZzfBR+J9RNxo246/6q2vI7cHLU9vYb+Pjypli7K18lRZshWXlXOxQqotd/rmmtfmV7JG89Qz0bIq167uV9/H5KwNm14LY/QrZkzlc3oPR2ITvOeKrFxaY26g2I+1ad18/aYF9rj3h8WHtq8qxies28mhaAUA/PMi3A2J/6ibaFVrGyW7NvXw/gmT10Mjyxjloxith0Ne46U0OtJQMmraOfELf+fRCuhGL8uuIYX9TPozlRDS/A7c00zzGTnHtT9vjNEnXx4zZL0+p5lw/yXFk8u4jWP9HmGMgYtd2VkpfT6RNXMK2AOgOfIxwPZ0COjWyTQDUefKdnZFY25H8dbK6xUmRKsKpqtrnxcqEQm7iT09wQLn69Wb74i1G/+AKzJPsbrwZ4g8taHFwHa7JRK7kaMyYB9t+Oxi18N701WcCFI8qfrj0ZjEcl9+w51ZGUEGbg8DlNErMpwqD8+M2IGC3bGbzrdiAp4pfABFR7J6BUOaTajesSCdLtGZ++L7joym/VRTDxlpaIVpfceSwwAk+nQ9bhL1NII/j2d+wgaqfHBy6cFOnPyA+ohb9333QDQLO7zhkfXveUUg2tqf2C9kDQ57CWWOpoEV/9ZVJ/bTIt2yqz7xwdTHsLR4eJXmP22CjBBItK8I5hzdwQ0BMVNezw/e4AtgVKpSWY43BGuzpXlJR+zvq+GZDlZSk6JU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:5;SRV:;IPV:CAL;SFV:SPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:OSPM;SFS:(13230022)(4636009)(39860400002)(396003)(346002)(136003)(376002)(451199015)(40470700004)(46966006)(36840700001)(2906002)(5660300002)(8936002)(41300700001)(4326008)(8676002)(70586007)(70206006)(478600001)(82740400003)(356005)(81166007)(40460700003)(186003)(6666004)(26005)(336012)(36756003)(1076003)(2616005)(6916009)(82310400005)(36860700001)(40480700001)(54906003)(316002)(83380400001)(426003)(47076005)(36900700001)(11215385002);DIR:OUT;SFP:1501; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:13:47.3931 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e78dc95d-ad04-436c-38c5-08dabb52825f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5964 Hi All, Please find the following patches to enable GICv3 for AArch32. This is a pre-requisite to support Xen on Cortex-R52 (AArch32-v8R system) Let me know your thoughts. Changes from v1 :- 1. Updated in the changelog for each of the patches. Ayan Kumar Halder (12): xen/Arm: vGICv3: Sysreg emulation is applicable for Aarch64 only xen/Arm: GICv3: Move the macros to compute the affnity level to arm64/arm32 xen/Arm: vreg: Support vreg_reg64_* helpers on Aarch32 xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32 xen/Arm: GICv3: Fix GICR_{PENDBASER, PROPBASER} emulation on 32-bit host xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32 xen/Arm: GICv3: Define ICH_LR_EL2 on AArch32 xen/Arm: GICv3: Define ICH_AP0R and ICH_AP1R for AArch32 xen/Arm: GICv3: Define GIC registers for AArch32 xen/Arm: GICv3: Use ULL instead of UL for 64bits xen/Arm: GICv3: Define macros to read/write 64 bit xen/Arm: GICv3: Enable GICv3 for AArch32 SUPPORT.md | 6 + xen/arch/arm/Kconfig | 4 +- xen/arch/arm/gic-v3-lpi.c | 8 +- xen/arch/arm/gic-v3.c | 132 ++++++++++----------- xen/arch/arm/include/asm/arm32/io.h | 21 ++++ xen/arch/arm/include/asm/arm32/processor.h | 5 + xen/arch/arm/include/asm/arm32/sysregs.h | 18 ++- xen/arch/arm/include/asm/arm64/processor.h | 8 ++ xen/arch/arm/include/asm/arm64/sysregs.h | 3 + xen/arch/arm/include/asm/cpregs.h | 69 +++++++++++ xen/arch/arm/include/asm/cpufeature.h | 1 + xen/arch/arm/include/asm/gic_v3_defs.h | 24 ++-- xen/arch/arm/include/asm/gic_v3_its.h | 2 +- xen/arch/arm/include/asm/processor.h | 6 - xen/arch/arm/include/asm/vreg.h | 88 ++++---------- xen/arch/arm/vgic-v3-its.c | 17 +-- xen/arch/arm/vgic-v3.c | 16 ++- 17 files changed, 255 insertions(+), 173 deletions(-)