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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id b12-20020adfe30c000000b00306423904d6sm3053844wrj.45.2023.05.05.10.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 10:57:12 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 44447875-eb6e-11ed-b226-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1683309433; x=1685901433; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=q1h9+sOy91h+3M0AKDC27QolVTLW8C6xg301Hs3wQXQ=; b=NUt+BCXAFaIMCWuvrEKzAzsu+FJJ0FZB1k8sG8goSYxw5RnMZSuDvCbxdo8aMCjwB8 FXzaSVlQQ5g81Ek0bfrH1Zf00cyXAi4RN++m14nbcMCFbdFQVc9A7W6/N9mQpNL8k4/Z EMw7vlgtIJrqy/I/QMDdx9a3MMIYdd7repEjY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683309433; x=1685901433; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=q1h9+sOy91h+3M0AKDC27QolVTLW8C6xg301Hs3wQXQ=; b=XFz9bxiDSE7pmes0mQN0QP4Hg/p5POeY5dmGGnL133UK2s2mnaPM8cOElMtEnccco2 1ESgywIjgjk6NQg/b35zZvxS079OnNEnlMTRg0J+BvHXHH28+zwnj4MImTn3ySwB0TmH tgRn3UIA5AryLktgjYK781K4rmwEi1exwLgUxNaogvPgkPAsaiAO/A+soNTf3vL9c7pF JbeXaCJQAJRmuUHPZUK3JcPVAhJA2jT94nxBkQckpFHlhZTkRZr3s2ARbwNNBqUkXX8x b9bvYFyn/gbm7qlTq8wckjj1OvmTJuJJd2f09EnlP3EDVdi4Wtj0KdmcIhB1TP7UF7K4 wZCg== X-Gm-Message-State: AC+VfDzovUQnLXlFiYoymaJfiV5wnyvi2UAMrTHiwwaYjbhNa0Jeaf0r wc57xCDFWm1ZLQo2vM0Ll2gpD9wz/I9jJHGP13g= X-Google-Smtp-Source: ACHHUZ7G8+HYT3oqu2wvuuAHP58jwcanfBtV62hU5W0nwG7NX2mhAIPVxD5VmNHQXpKHIg0M18Bqug== X-Received: by 2002:a7b:c44c:0:b0:3ed:f5b5:37fc with SMTP id l12-20020a7bc44c000000b003edf5b537fcmr1589134wmi.1.1683309432993; Fri, 05 May 2023 10:57:12 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Wei Liu , Anthony PERARD , Juergen Gross , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 0/3] Add CpuidUserDis support Date: Fri, 5 May 2023 18:57:02 +0100 Message-Id: <20230505175705.18098-1-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Nowadays AMD supports trapping the CPUID instruction from ring3 to ring0, (CpuidUserDis) akin to Intel's "CPUID faulting". There is a difference in that the toggle bit is in a different MSR and the support bit is in CPUID itself rather than yet another MSR. This patch enables AMD hosts to use it when supported in order to provide correct CPUID contents to PV guests. Also allows HVM guests to use CpuidUserDis via emulated "CPUID faulting". Patch 1 merely adds definitions to various places in CPUID and MSR Patch 2 adds support for CpuidUserDis, hooking it in the probing path and the context switching path. Patch 3 enables HVM guests to use CpuidUserDis as if it was CPUID faulting, saving an avoidable roundtrip through the hypervisor at fault handling. Alejandro Vallejo (3): x86: Add AMD's CpuidUserDis bit definitions x86: Add support for CpuidUserDis x86: Use CpuidUserDis if an AMD HVM guest toggles CPUID faulting tools/libs/light/libxl_cpuid.c | 1 + tools/misc/xen-cpuid.c | 2 + xen/arch/x86/cpu/amd.c | 29 +++++++++++- xen/arch/x86/cpu/common.c | 51 +++++++++++---------- xen/arch/x86/cpu/intel.c | 11 ++++- xen/arch/x86/include/asm/amd.h | 1 + xen/arch/x86/include/asm/msr-index.h | 1 + xen/arch/x86/msr.c | 9 +++- xen/include/public/arch-x86/cpufeatureset.h | 1 + 9 files changed, 79 insertions(+), 27 deletions(-)