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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id s9-20020a5d5109000000b002ffbf2213d4sm14754606wrt.75.2023.05.09.09.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 May 2023 09:43:39 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a7fb8427-ee88-11ed-b229-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1683650621; x=1686242621; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=6Vv9h8xRR34WXMgEze0CmFq4k7f1bgK9vFoprNoHdzc=; b=DSNgs0hmVkJMJlA6yBYq9TF7QVy7IfG0z9GULd8GywiDk2FKO04piCfpzWMnSrV65/ 0Dx/auYQzpE38dxMuoz3BE8Sat8RAQddKRB5IpenwTa6fSShArj4Qc/7zu7+qHUqX4HE 9KQyOMVQMq5/Erb6CZvgu8xWl+ID87LEoFqcY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683650621; x=1686242621; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6Vv9h8xRR34WXMgEze0CmFq4k7f1bgK9vFoprNoHdzc=; b=j0yIIbCZG7BktbBLhWtq2qt4L6hg/I8e3QyQZJRpsS3gRYo1K25nAT5fZcg2ujFLFp 6MQZ5NlRHfuMnExHqlkjjB2Cm8hEVc7FeiygvpHoTnOIzgKwW0DzDsQczk8PwruqFCIf nIOhHmBCsGmN7Ak39yXzeBEzKDTr1l2okIEmq3oZYwfQJN+FDwa9rMvZ8on4ZaUSyXmv IJ+Ytwfi9hyIHOChnZN7qi7WsCex+FZGwr+oRfiyKJRquGZCvstwnX8SGVQbw3KbpOo4 MEui0KscKmxPS2G6Oj0XqWqZdKt0GpoDnmE0HZLWUn9Kc3lA+FxLAfIUik2gh1V8h2Ya aLAw== X-Gm-Message-State: AC+VfDySimX1gV8RaTfxpHAEpXLprQ+eoFnTUU5NZY9W4/M3f9invn5H XGb9QF45q29PPNbj9eh4wuka4tYC84bmbcPiHgo= X-Google-Smtp-Source: ACHHUZ7zPKxYr8ChuNd7x3xyoGnskZRptPhUxOU9LOoGvv57zoOdccEaZNbbEjBeGCUKb+Os2c74EQ== X-Received: by 2002:adf:feca:0:b0:2fb:92c7:b169 with SMTP id q10-20020adffeca000000b002fb92c7b169mr14253235wrs.10.1683650620761; Tue, 09 May 2023 09:43:40 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Wei Liu , Anthony PERARD , Juergen Gross , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH v2 0/3] Add CpuidUserDis support Date: Tue, 9 May 2023 17:43:33 +0100 Message-Id: <20230509164336.12523-1-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 v2: * Style changes * Remove v1/patch3: HVM not to be addressed by this series * Adds one patch between v1/patch1 and v1/patch2 with the vendor-specific refactor of probe_cpuid_faulting() Nowadays AMD supports trapping the CPUID instruction from ring>0 to ring0, (CpuidUserDis) akin to Intel's "CPUID faulting". There is a difference in that the toggle bit is in a different MSR and the support bit is in CPUID itself rather than yet another MSR. This patch enables AMD hosts to use it when supported in order to provide correct CPUID contents to PV guests. Patch 1 merely adds definitions to various places in CPUID and MSR Patch 2 moves vendor-specific code on probe_cpuid_faulting() to amd.c/intel.c Patch 3 adds support for CpuidUserDis, hooking it in the probing path and the context switching path. Alejandro Vallejo (3): x86: Add AMD's CpuidUserDis bit definitions x86: Refactor conditional guard in probe_cpuid_faulting() x86: Add support for CpuidUserDis tools/libs/light/libxl_cpuid.c | 1 + tools/misc/xen-cpuid.c | 2 + xen/arch/x86/cpu/amd.c | 28 ++++++++++- xen/arch/x86/cpu/common.c | 51 +++++++++++---------- xen/arch/x86/cpu/intel.c | 12 ++++- xen/arch/x86/include/asm/amd.h | 1 + xen/arch/x86/include/asm/msr-index.h | 1 + xen/include/public/arch-x86/cpufeatureset.h | 1 + 8 files changed, 71 insertions(+), 26 deletions(-)