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With it in place, here are some examples from various generations of Intel hardware: BDX Raw BDX Host BDX HVM Max rsba KBL Raw rsba misc-pkg-ctrl energy-ctrl KBL Host rsba misc-pkg-ctrl energy-ctrl KBL HVM Max rsba SKX Raw rsba misc-pkg-ctrl energy-ctrl SKX Host rsba misc-pkg-ctrl energy-ctrl SKX HVM Max rsba CFL Raw rdcl-no eibrs skip-l1dfl mds-no tsx-ctrl misc-pkg-ctrl energy-ctrl fb-clear CFL Host rdcl-no eibrs rsba skip-l1dfl mds-no tsx-ctrl misc-pkg-ctrl energy-ctrl fb-clear rrsba CFL HVM Max rdcl-no eibrs rsba mds-no fb-clear rrsba CLX Raw rdcl-no eibrs skip-l1dfl mds-no tsx-ctrl misc-pkg-ctrl energy-ctrl sbdr-ssdp-no psdp-no fb-clear rrsba CLX Host rdcl-no eibrs rsba skip-l1dfl mds-no tsx-ctrl misc-pkg-ctrl energy-ctrl sbdr-ssdp-no psdp-no fb-clear rrsba CLX HVM Max rdcl-no eibrs rsba mds-no sbdr-ssdp-no psdp-no fb-clear rrsba SPR Raw rdcl-no eibrs skip-l1dfl mds-no if-pschange-mc-no tsx-ctrl taa-no misc-pkg-ctrl energy-ctrl SPR Host rdcl-no eibrs rsba skip-l1dfl mds-no if-pschange-mc-no tsx-ctrl taa-no misc-pkg-ctrl energy-ctrl rrsba SPR HVM Max rdcl-no eibrs rsba mds-no if-pschange-mc-no taa-no rrsba Of note: * The SPR CPU is pre-release and didn't get the MMIO ucode in the end (sbdr-ssdp-no psdp-no fb-clear). * SKX/KBL enumerate RSBA following the energy filtering microcode. Prior to that, they don't enumerate MSR_ARCH_CAPS at all. * CFL and SPR fails to enumerate both RSBA and RRSBA. CLX fails to enumerate RSBA. These should be addressed in due course. Andrew Cooper (4): x86/spec-ctrl: Rename retpoline_safe() to retpoline_calculations() x86/spec-ctrl: Synthesize missing RSBA/RRSBA bits x86/cpu-policy: Rearrange guest_common_default_feature_adjustments() x86/cpu-policy: Derive {,R}RSBA for guest policies xen/arch/x86/cpu-policy.c | 59 ++++++++++++++------ xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/spec_ctrl.c | 78 +++++++++++++++++++++------ xen/tools/gen-cpuid.py | 5 +- 4 files changed, 111 insertions(+), 32 deletions(-)