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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id v11-20020a170906564b00b00992c4103cb5sm307727ejr.129.2023.06.29.08.26.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 08:26:58 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 63795e92-1691-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1688052418; x=1690644418; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=l6KfuSFi0sd3KAdUkh7aqTuNtWs7UyItOcyC31/eBJQ=; b=YXk8puFQMQt0SZdpYEw5mpye/r3qGrrkX0euwAguHNOHDnBDGgbHIR64wDSWCyossB 8AQqz87aCbKJS86uG2WMplMB6bT8SpqnRMBnbm9SXumJ9SJLpcDF6bU7NdJT8DjSMO0h egXoSZEOMSNFDuk1u2ao+ZEXIKCTL+5sYeVL8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688052418; x=1690644418; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=l6KfuSFi0sd3KAdUkh7aqTuNtWs7UyItOcyC31/eBJQ=; b=Vxm8DbKW5XNM7IPiP1Kab04KPd64osQsPoVpH6pM0ylbJ+CwhqnDaNZ8Uguy0N8d9b i0EXPfZNhY4fw/qUw/8+i1/OfmxsNDxvcya/y3gdE9sidtyQZl0tD2PkoVqgTKusSj73 xgCfKAYqYFA9oWLjaVfDEmzgRvr5RzjN1BbpaCfiQBeFaeKfsChTC5zK9J2A+u6Rdz5L 443BIroQ/0OMsz5bMgGkhihO4moK0y71v3wXSk3J21OYBVGnWiI7Y22IBVD+FRzOVeOH EymrZApaD7XH+1Tp63cgzvT2HpNnjd6ZgrBOYVB1jcOkk4KzRW6c/Jsn+q9QOsXXmh/Q eoLA== X-Gm-Message-State: AC+VfDzvWXkGi4lMPYao3frEDHIprQy4LzCLjBE1i3PleKgZe6ph69w3 G2bkvoojmrm8t6O4uErt4OuxZf68Y8wGqNZ5yBc= X-Google-Smtp-Source: ACHHUZ6s3CcOimOib4442RrBY2i+e6XzMZuIKN8VvNZ5RJ0UzKLVVBZYtaZJklh8XUbshnwQ/xTxRA== X-Received: by 2002:a17:907:708:b0:97b:956f:e6b5 with SMTP id xb8-20020a170907070800b0097b956fe6b5mr35221272ejb.23.1688052418353; Thu, 29 Jun 2023 08:26:58 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v5 0/4] Prevent attempting updates known to fail Date: Thu, 29 Jun 2023 16:26:52 +0100 Message-Id: <20230629152656.12655-1-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Under certain conditions a CPU may not be able to perform microcode updates even if hardware exists to that effect. In particular: * If Xen runs under certain hypervisors they won't allow microcode updates, and will signal this fact by reporting a microcode revision of -1. * If the DIS_MCU_LOAD bit is set, which is expected in some baremetal clouds where the owner may not trust the tenant, then the CPU is not capable of loading new microcode. This series adds logic so that in both of these cases we don't needlessly attempt updates that are not going to succeed. Patch summary: Patch 1 Introduces the logic to print the microcode revision if at all possible Patch 2 Ignores microcode facilities when the current microcode revision is -1 Patch 3 Moves the MSR_ARCH_CAPS read in tsx_init() to early_cpu_init() and early_microcode_init() Patch 4 Adds the logic to detect microcode updates being disabled on Intel. Alejandro Vallejo (4): x86/microcode: Allow reading microcode revision even if it can't be updated x86/microcode: Ignore microcode loading interface for revision = -1 x86: Read MSR_ARCH_CAPS immediately after early_microcode_init() x86/microcode: Disable microcode update handler if DIS_MCU_UPDATE is set xen/arch/x86/cpu/common.c | 23 ++++++++++++------ xen/arch/x86/cpu/microcode/core.c | 35 ++++++++++++++++++++++----- xen/arch/x86/cpu/microcode/intel.c | 13 ++++++++++ xen/arch/x86/cpu/microcode/private.h | 7 ++++++ xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/msr-index.h | 5 ++++ xen/arch/x86/setup.c | 2 +- xen/arch/x86/tsx.c | 16 +++--------- 8 files changed, 75 insertions(+), 27 deletions(-)