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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= , Jiqian Chen , Mykyta Poturai Subject: [PATCH v17 0/2] PCI devices passthrough on Arm, part 3 Date: Tue, 11 Mar 2025 16:13:26 -0400 Message-ID: <20250311201330.365499-1-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.48.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE1B:EE_|SA5PPF8ECEC29A9:EE_ X-MS-Office365-Filtering-Correlation-Id: c3332fb0-b731-4853-fa13-08dd60d9339a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?1V9VGIUS2QxszHkwXcgP+GxgyzudUwy?= =?utf-8?q?UMo94muEyFeFHh8IEH4xNSSFnRlIiMeHqBYar6udta3offormNoNkD4xhuAJOBJtS?= =?utf-8?q?LiVTRdJddtIrD3g9FDqS5DESRxZulud33c3UNrGRnvAbqTLrY4LNB2lubksUKJm+P?= =?utf-8?q?vpjOmw1BweXRXMjUn9QMPRtUyLfvKqpyN70chRk9CAvR2J9eQ07Vv6a3azRKdCCnE?= =?utf-8?q?//rHAAdDd9N2QHF6nReojDm6hjTgQZ8A5ZOVZZua2MiNDi1Z/CCaPtx4KcS2LX2Vz?= =?utf-8?q?4QK01cOIEICOs5NeSwPYr51ahl9ZMntCVu95OlWkcBCubd3AlqDOU0K2vw1kRejGT?= =?utf-8?q?2eDoQH8AKNocZrNINsVY3M9K0Wk00SxlwoRh67WGoN5U65lHmhJuVYXKzpecW0Uat?= =?utf-8?q?a+O28KWxdUofsjDvXAHXztmEcwV2QZIvQzVeoj5roe3ohP+WFa3HSH+3iXDSbO+6d?= =?utf-8?q?8GTQfAYQRx/iFFWxxSYj/N6hzQT+j02sKSxwtlHRMbPRkDY8I0911/XpxCi7R63b+?= =?utf-8?q?2Ar2sHNjpw9q/n1iuBcdq9g6BhHuoAwpomS1mxkEtIrYR9zjNdEcgw5V12ZcurjMG?= =?utf-8?q?fgRMxI7yA6lfAs08IemJTrp++PYN1klxQDOxlKvi5wHHTF8akPu5KHRlzC1XadES8?= =?utf-8?q?yMVwImzWEbiKOk1CwH5a8yZ4lL7iOSHfIvQ34ulzCS1B2OJ8us0lB0LgVaSLLj4Mf?= =?utf-8?q?Ydx9SggWbZEhMbjE3weIrw08tRac7CzGeTFlkP5JdEdVAd/ViPvuRUxh8JSmjI/RP?= =?utf-8?q?cWQfqPHrTYT1SjtIBWTriigFkYpBhmw2iJi+5vkowQdaV9ZnTS9Ay6EjKJM29Qpi8?= =?utf-8?q?lhbNAJLQhZlfKRqNB3zAxGLLbL36mLi+sRTWjTQ1KGR76erzWd0mYBf3FbagQqxfs?= =?utf-8?q?6I99/Ni9vHNzAfJTgSXlxcpflGMfolucIykeITTn6L/WYKwv01pf/dzxkm6y0UUEJ?= =?utf-8?q?NMcRRhOtOAMF+Dn4C9xnJUtROuku3LzQdwinkQGGsQCotrTl/yutfeFdLmbgLT7sL?= =?utf-8?q?r9iX0dc7CWH4n7Zu7bxHw5x8gPtDQm7tXWqanaAQTwecyjpmGjNty9wcnYzKxg6wb?= =?utf-8?q?wVY5zeKBHpW7mX2+xu/+Je/U7+VTx+iwMnLEPPilVv2JTxkLr0NunwjrhayR7KKuC?= =?utf-8?q?VTwQiTpr9mOnAEHUsSI73xSJBnjg+dLLVV9U4ms11mxvj1u73VEc5BbZlyj3IdAIk?= =?utf-8?q?rZu8XALL/W8CanG7ORse5fDi5QN5kyMrjMVvJFQXl+apQn1gecR0FV6vTzUOsDFCM?= =?utf-8?q?uJObrS/YlTzklp9suctUU808E4morJ2d+nrC+ysFKjwJOmxx/mH4pewgh9UuAV7Z9?= =?utf-8?q?ULIWVufYU8BZuZ15qqywFx1Jwnm9Kc5VN+G6fsDIkSFHW92ZeSP70bEze/Ksw7zWt?= =?utf-8?q?unpAV0PoHeIBORQTwGz9NRCqb51dET9Bc9VCPqq37WEcG541/Ic/eY=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2025 20:13:34.4879 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3332fb0-b731-4853-fa13-08dd60d9339a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF8ECEC29A9 This is next version of vPCI rework. Aim of this series is to prepare ground for introducing PCI support on ARM platform. in v17: - add ("xen/arm: check read handler behavior") - drop ("xen/arm: account IO handlers for emulated PCI MSI-X") as it should wait for future work - drop committed patches in v16: - minor updates - see individual patches in v15: - reorder so ("arm/vpci: honor access size when returning an error") comes first in v14: - drop first 9 patches as they were committed - updated ("vpci/header: emulate PCI_COMMAND register for guests") in v13: - drop ("xen/arm: vpci: permit access to guest vpci space") as it was unnecessary in v12: - I (Stewart) coordinated with Volodomyr to send this whole series. So, add my (Stewart) Signed-off-by to all patches. - The biggest change is to re-work the PCI_COMMAND register patch. Additional feedback has also been addressed - see individual patches. - Drop ("pci: msi: pass pdev to pci_enable_msi() function") and ("pci: introduce per-domain PCI rwlock") as they were committed - Rename ("rangeset: add rangeset_empty() function") to ("rangeset: add rangeset_purge() function") - Rename ("vpci/header: rework exit path in init_bars") to ("vpci/header: rework exit path in init_header()") in v11: - Added my (Volodymyr) Signed-off-by tag to all patches - Patch "vpci/header: emulate PCI_COMMAND register for guests" is in intermediate state, because it was agreed to rework it once Stewart's series on register handling are in. - Addressed comments, please see patch descriptions for details. in v10: - Removed patch ("xen/arm: vpci: check guest range"), proper fix for the issue is part of ("vpci/header: emulate PCI_COMMAND register for guests") - Removed patch ("pci/header: reset the command register when adding devices") - Added patch ("rangeset: add rangeset_empty() function") because this function is needed in ("vpci/header: handle p2m range sets per BAR") - Added ("vpci/header: handle p2m range sets per BAR") which addressed an issue discovered by Andrii Chepurnyi during virtio integration - Added ("pci: msi: pass pdev to pci_enable_msi() function"), which is prereq for ("pci: introduce per-domain PCI rwlock") - Fixed "Since v9/v8/... " comments in changelogs to reduce confusion. I left "Since" entries for older versions, because they were added by original author of the patches. in v9: v9 includes addressed commentes from a previous one. Also it introduces a couple patches from Stewart. This patches are related to vPCI use on ARM. Patch "vpci/header: rework exit path in init_bars" was factored-out from "vpci/header: handle p2m range sets per BAR". in v8: The biggest change from previous, mistakenly named, v7 series is how locking is implemented. Instead of d->vpci_rwlock we introduce d->pci_lock which has broader scope, as it protects not only domain's vpci state, but domain's list of PCI devices as well. As we discussed in IRC with Roger, it is not feasible to rework all the existing code to use the new lock right away. It was agreed that any write access to d->pdev_list will be protected by **both** d->pci_lock in write mode and pcidevs_lock(). Read access on other hand should be protected by either d->pci_lock in read mode or pcidevs_lock(). It is expected that existing code will use pcidevs_lock() and new users will use new rw lock. Of course, this does not mean that new users shall not use pcidevs_lock() when it is appropriate. Changes from previous versions are described in each separate patch. Oleksandr Andrushchenko (1): xen/arm: translate virtual PCI bus topology for guests Stewart Hildebrand (1): xen/arm: check read handler behavior xen/arch/arm/io.c | 2 ++ xen/arch/arm/vpci.c | 43 +++++++++++++++++++++++++++++++---------- xen/drivers/vpci/vpci.c | 26 +++++++++++++++++++++++++ xen/include/xen/vpci.h | 12 ++++++++++++ 4 files changed, 73 insertions(+), 10 deletions(-) base-commit: be59cceb2dbbea3815f35f6982aac6d2ab1b10b7