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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?kVcK8G3hgr8kNBLT+RHiHIxHNhYF?= =?utf-8?q?c5ok8f1/049B57lzl3ItfiYrq12Wqb7htVw4u0fJWxk3h2tFdJSWz32orgju19u+p?= =?utf-8?q?2pcKBOu7yAqUULhhQ+mqjgoAi7zOWAzvtA35NZGf/HSiXZtzaYns+iYgc49pOWHOl?= =?utf-8?q?qVzVXBJ9SHwt67SwmjEI1FhQ28mKdymsj9RqnYNFf3kbdTfL9oRbUXH2QrUhGpwxi?= =?utf-8?q?VbPc3AOy2PEzxKkBPVvjojvz32jkpyMXvh3SBVRv1vJDD4JwIV+CzDLMC+pt5iezI?= =?utf-8?q?F9D81iBcAaiWrDe5Uip+ohpOjhkGhnoX6id9S4aC60eRZsyDsiTiIp5959AtS5cUR?= =?utf-8?q?uvHJznb6OcJZqZIeevMAon6Gze7QorkL6NEpMqPL50GHM4g+wXONEau1lEfiEDP71?= =?utf-8?q?iExAk4zaeadS5CL/Z/k5Fw99AHvHvDcLLsYtB5Vhm+63/0t9Id3MrmG5nrrgiIZrc?= =?utf-8?q?C91y2nxcrspYkYkwOqjYRRZBPxUv7lD/iXBgJBCng8rYwcMZB3aj9djYnqfoxusyq?= =?utf-8?q?j8W1AWbsrAAEiDnSHzv+7l/uQRBWWhXSfhOYYkaA85bT6Ulu6jVLxNZ/BnItrz5ss?= =?utf-8?q?FEhY76Ipfixv87iYYb6prShh34BMjtJEvZmMojRJuzs+/bYx3/EDt+OEm7lUTyjYR?= =?utf-8?q?0gMVAWHAqXJxOslP/h6ZpuYU2g1drySFQL8sNsRHYgb5yG8yABtcBRHkqBSyj9S79?= =?utf-8?q?BBvBWodZCr6/NfXqDN7tZJeOn2iX8WtNpYn/EM1zklvwG8KpYvQazctAhWWx5CI4r?= =?utf-8?q?kGJ4Kz87L+gDL31uQ9RKxnzh3HrOFps3fOrbfxlbeZiIRs7OG2JqRWtANyT7gjHr2?= =?utf-8?q?18iv4G9you/lTRegxhDTWSnLgFATnC+Xdh/sUI1SfDJBBz2L3uHd6/WF1BmvpLCdL?= =?utf-8?q?9tg0jzh7Cl6U7ULR0qKf6xDKNgB/06bMqkUqNdsvnt8iFMVU2wK2q24A+dO0wBE4T?= =?utf-8?q?R1jNjff+rMLyvc5RiiY3Ck7W1Pm6zTVkxWTG65/sgYMhJqiqMv/BFcJM0U8xcOsS/?= =?utf-8?q?R1emDjXGSa0ARWY+QJ9gtI+2FmCirpB26XZkVrT/quKgwoxYe2sJ4hoUAkVrMKtd7?= =?utf-8?q?KiN50PNDAEcbTVZ0m7an3jAK2mlJ5C3j6tRlKddJvx10FKLoqsIB5Ys7PWqFJjqAg?= =?utf-8?q?K4vzcOu8duHFsx8VaO1rLWW83yLMU8bJR296H70xoRAgU8s8OXEp+0S4cUZ6zFvS/?= =?utf-8?q?cMcxOy6PQTJlkWRNMSh+JzBJ0UP0qYCvwgxFba2ajHNTA1E0ZuvVSQxeuK6OTl9MG?= =?utf-8?q?LP/AVBuJ6TNEsg3WP0OqxpNSOKZlRajh4poVhPKxocCCx0uYlr40BQnLJxmzLi+Q/?= =?utf-8?q?ROsJP8Fvjq+QUfIZj0MitHmms4tmBhiGJeVOKqF1P0GO1Vugt07kllt5DwjsMY0AV?= =?utf-8?q?bGARH3V2CrjT+3m2vUk1/ASe0A5K3qqOeMmwPZiB1o7otkd6zguDVzeM9BIHUfz9l?= =?utf-8?q?yZRp72OKbMPZJa7ztk88wXinmiBN7xxOnYC/TjALxBAskZ+5CUuJHbS41USQoIUm0?= =?utf-8?q?t+zGdKtMdr7pIp7hO2heLifwBBAsXph0TIXdbY5AJWz/M1sxuXkdh82R6djntW5yj?= =?utf-8?q?fhS4H3nciPr2gt/Y15EwJepS2dFOqjxBt22zTMDNDk3l8kLst5IL1Nht4iISyCKKt?= =?utf-8?q?B0KMAfURVbZ7L08LTlHvTDERIAnXif6Q=3D=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: a0478d19-7f98-47b3-3847-08da2695a8b6 X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8616.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2022 08:29:05.0249 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wiClTMN3XfXlIAmcWo5dB/Cr6/ET1LEY0CgJ+o3owA0O5RiaZUsJqmGVALtWTW2WShlCOOw2YVVEu1l8nLUbEg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8021 For a long time we've been rather inefficient with IOMMU page table management when not sharing page tables, i.e. in particular for PV (and further specifically also for PV Dom0) and AMD (where nowadays we never share page tables). While up to about 2.5 years ago AMD code had logic to un-shatter page mappings, that logic was ripped out for being buggy (XSA-275 plus follow-on). This series enables use of large pages in AMD and Intel (VT-d) code; Arm is presently not in need of any enabling as pagetables are always shared there. It also augments PV Dom0 creation with suitable explicit IOMMU mapping calls to facilitate use of large pages there. Depending on the amount of memory handed to Dom0 this improves booting time (latency until Dom0 actually starts) quite a bit; subsequent shattering of some of the large pages may of course consume some of the saved time. Known fallout has been spelled out here: https://lists.xen.org/archives/html/xen-devel/2021-08/msg00781.html There's a dependency on 'PCI: replace "secondary" flavors of PCI_{DEVFN,BDF,SBDF}()', in particular by patch 8. Its prereq patch still lacks an Arm ack, so it couldn't go in yet. I'm inclined to say "of course" there are also a few seemingly unrelated changes included here, which I just came to consider necessary or at least desirable (in part for having been in need of adjustment for a long time) along the way. Some of these changes are likely independent of the bulk of the work here, and hence may be fine to go in ahead of earlier patches. See individual patches for details on the v4 changes. 01: AMD/IOMMU: correct potentially-UB shifts 02: IOMMU: simplify unmap-on-error in iommu_map() 03: IOMMU: add order parameter to ->{,un}map_page() hooks 04: IOMMU: have iommu_{,un}map() split requests into largest possible chunks 05: IOMMU/x86: restrict IO-APIC mappings for PV Dom0 06: IOMMU/x86: perform PV Dom0 mappings in batches 07: IOMMU/x86: support freeing of pagetables 08: AMD/IOMMU: walk trees upon page fault 09: AMD/IOMMU: return old PTE from {set,clear}_iommu_pte_present() 10: AMD/IOMMU: allow use of superpage mappings 11: VT-d: allow use of superpage mappings 12: IOMMU: fold flush-all hook into "flush one" 13: IOMMU/x86: prefill newly allocate page tables 14: x86: introduce helper for recording degree of contiguity in page tables 15: AMD/IOMMU: free all-empty page tables 16: VT-d: free all-empty page tables 17: AMD/IOMMU: replace all-contiguous page tables by superpage mappings 18: VT-d: replace all-contiguous page tables by superpage mappings 19: IOMMU/x86: add perf counters for page table splitting / coalescing 20: VT-d: fold iommu_flush_iotlb{,_pages}() 21: VT-d: fold dma_pte_clear_one() into its only caller While not directly related (except that making this mode work properly here was a fair part of the overall work), at this occasion I'd also like to renew my proposal to make "iommu=dom0-strict" the default going forward. It already is not only the default, but the only possible mode for PVH Dom0. Jan