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[46.204.108.92]) by smtp.gmail.com with ESMTPSA id a25-20020a05651c031900b00295a8d1ecc7sm50489ljp.18.2023.02.24.03.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 03:35:09 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4bd9b731-b437-11ed-88bb-e56d68cac8db DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=ECAcOZyAZg3Dpbh3eSLd5IFMQTfPPWRvoFGodXIgSFw=; b=Iofvxq4DQPxocp3qHrjr3PYdeA4JbyjCZArwGn0tGHCLpZqYicU5bRku/Pxq5rzrUp VpMDGEzRdFW/c9kyIXmWMJyLs98eM6Fhs0lHJs03XzqqfSiW9oxYus/eeAjZE9tsl0I6 LXpt3kXN0BNZjuMGRSI72vSOE6FqPeFFUk9wFPE1OjgPRGGsQlUKcPd1FR5HrSWPqwTm zKRAFYw9q3Eu651L78RRmY18ppuAVW4IRt/FiezUnlax7bJbMYG5tHlig4fnXZfFaHQy hca/Ow07pou/lngYc0j9naKpAJ+Sdbd4XoXny2yu1ZGzFDzQ7iK1Rm6jO7mJpyxFvZpS FlPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ECAcOZyAZg3Dpbh3eSLd5IFMQTfPPWRvoFGodXIgSFw=; b=YwJriQpQINVhE2L8UlIWviz2Jd0q8H0ulQUIL92URMnH2qWleMHqtZxsc0ky3zQcK8 5A686NUjQRhqdWzkz9OoZLkx8ehPx0hhqf4BooDTqY9So+uoDaFIHHOyWd12Mq6141Jc 7WIa6HN9rg0cQHDgT56nCcOLfQIQcv8a7VRl7ppYlBOxnYGMXqmtFH+93qiO1SvobEwu 6PhpHvPzLg1Ce2UoP6uPQmjK/Pe76yCRHNZosrR5Qijefgx7+lwvuSBIQ6ec+0z14ej1 gowp0GUcGOzkcXLY2Y2wH2TIUe/+ILvo743+rjvj/u0VxXvTkmvHRgpX7wnWPQ3kWLie kJIw== X-Gm-Message-State: AO0yUKVNJxHsPLyNeKU2OecR0Q42gDD9pEWvqkqPV5FId7QT/JHG4kiH +IAMW2i+2r90lr6T7crJWAmHGoJ9AZI= X-Google-Smtp-Source: AK7set8TfNbsO2VU0reGOpxaezKx6LgtuB3hEs+cSb0Mugc2HEDpDislI8aa1WVXzK7d/NgVSur0Bw== X-Received: by 2002:a2e:bc0e:0:b0:294:6b9a:baa7 with SMTP id b14-20020a2ebc0e000000b002946b9abaa7mr8551645ljf.38.1677238510173; Fri, 24 Feb 2023 03:35:10 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Julien Grall , Jan Beulich , Andrew Cooper , Stefano Stabellini , Gianluca Guida , Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis , Doug Goldstein Subject: [PATCH v4 0/5] RISCV basic exception handling implementation Date: Fri, 24 Feb 2023 13:35:00 +0200 Message-Id: X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 The patch series is based on [introduce generic implementation of macros from bug.h] which hasn't been commited yet. The patch series provides a basic implementation of exception handling. It can do only basic things such as decode a cause of an exception, save/restore registers and execute "wfi" instruction if an exception can not be handled. To verify that exception handling works well it was implemented macros from such as BUG/WARN/run_in_exception/assert_failed. The implementation of macros is used "ebreak" instruction and set up bug frame tables for each type of macros. Also it was implemented register save/restore to return and continue work after WARN/run_in_exception. Not all functionality of the macros was implemented as some of them require hard-panic the system which is not available now. Instead of hard-panic 'wfi' instruction is used but it should be definitely changed in the neareset future. It wasn't implemented show_execution_state() and stack trace discovering as it's not necessary now. --- Changes in V4: - Rebase the patch series on top of new version of [introduce generic implementation of macros from bug.h] patch series. - Update the cover letter message as 'Early printk' was merged and the current one patch series is based only on [introduce generic implementation of macros from bug.h] which hasn't been commited yet. - The following patches of the patch series were merged to staging: [PATCH v3 01/14] xen/riscv: change ISA to r64G [PATCH v3 02/14] xen/riscv: add header [PATCH v3 03/14] xen/riscv: add header [PATCH v3 05/14] xen/riscv: introduce empty [PATCH v3 06/14] xen/riscv: introduce empty [PATCH v3 07/14] xen/riscv: introduce exception context [PATCH v3 08/14] xen/riscv: introduce exception handlers implementation [PATCH v3 10/14] xen/riscv: mask all interrupts - Fix addressed comments in xen-devel mailing list. --- Changes in V3: - Change the name of config RISCV_ISA_RV64IMA to RISCV_ISA_RV64G as instructions from Zicsr and Zifencei extensions aren't part of I extension any more. - Rebase the patch "xen/riscv: introduce an implementation of macros from " on top of patch series [introduce generic implementation of macros from bug.h] - Update commit messages --- Changes in V2: - take the latest riscv_encoding.h from OpenSBI, update it with Xen related changes, and update the commit message with "Origin:" tag and the commit message itself. - add "Origin:" tag to the commit messag of the patch [xen/riscv: add header]. - Remove the patch [xen/riscv: add early_printk_hnum() function] as the functionality provided by the patch isn't used now. - Refactor prcoess.h: move structure offset defines to asm-offsets.c, change register_t to unsigned long. - Refactor entry.S to use offsets defined in asm-offsets.C - Rename {__,}handle_exception to handle_trap() and do_trap() to be more consistent with RISC-V spec. - Merge the pathc which introduces do_unexpected_trap() with the patch [xen/riscv: introduce exception handlers implementation]. - Rename setup_trap_handler() to trap_init() and update correspondingly the patches in the patch series. - Refactor bug.h, remove bug_instr_t type from it. - Refactor decode_trap_cause() function to be more optimization-friendly. - Add two new empty headers: and as they are needed to include which provides ARRAY_SIZE and other macros. - Code style fixes. --- Oleksii Kurochko (5): xen/riscv: introduce decode_cause() stuff xen/riscv: introduce trap_init() xen/riscv: introduce an implementation of macros from xen/riscv: test basic handling stuff automation: modify RISC-V smoke test automation/scripts/qemu-smoke-riscv64.sh | 2 +- xen/arch/riscv/include/asm/bug.h | 48 +++++ xen/arch/riscv/include/asm/processor.h | 2 + xen/arch/riscv/include/asm/traps.h | 1 + xen/arch/riscv/setup.c | 21 +++ xen/arch/riscv/traps.c | 219 ++++++++++++++++++++++- xen/arch/riscv/xen.lds.S | 10 ++ 7 files changed, 301 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/include/asm/bug.h