[for,4.21,v6,0/2] RISC-V runtime detection of extenstions

Message

Oleksii Kurochko Feb. 12, 2025, 4:50 p.m. UTC

Based on riscv,isa property of device tree file parse extenstions which are
available in CPU.

As a part of this feature, drop CONFIG_RISCV_ISA_RV64G and explicitly use
extensions 'i', 'm', 'a', 'zicsr', 'zifencei' as they are necessary for a work
if Xen and it should be true not only for RISC-V 64 (but also for 32 and 128).

Oleksii Kurochko (2):
  xen/riscv: drop CONFIG_RISCV_ISA_RV64G
  xen/riscv: identify specific ISA supported by cpu

 xen/arch/riscv/Kconfig                  |  10 -
 xen/arch/riscv/Makefile                 |   1 +
 xen/arch/riscv/arch.mk                  |   9 +-
 xen/arch/riscv/cpufeature.c             | 502 ++++++++++++++++++++++++
 xen/arch/riscv/include/asm/cpufeature.h |  59 +++
 xen/arch/riscv/setup.c                  |   3 +
 6 files changed, 572 insertions(+), 12 deletions(-)
 create mode 100644 xen/arch/riscv/cpufeature.c
 create mode 100644 xen/arch/riscv/include/asm/cpufeature.h