From patchwork Wed Feb 5 09:43:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 11365983 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1784D92A for ; Wed, 5 Feb 2020 09:44:17 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F27E72082E for ; Wed, 5 Feb 2020 09:44:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F27E72082E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1izHDG-0000Ho-Em; Wed, 05 Feb 2020 09:43:14 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1izHDE-0000He-KQ for xen-devel@lists.xenproject.org; Wed, 05 Feb 2020 09:43:12 +0000 X-Inumbo-ID: ec28c7a8-47fb-11ea-ad98-bc764e2007e4 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id ec28c7a8-47fb-11ea-ad98-bc764e2007e4; Wed, 05 Feb 2020 09:43:11 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 0B8BBAF4E; Wed, 5 Feb 2020 09:43:11 +0000 (UTC) From: Jan Beulich To: "xen-devel@lists.xenproject.org" References: Message-ID: <056a856a-147e-612b-d476-50be80406581@suse.com> Date: Wed, 5 Feb 2020 10:43:18 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.4.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US Subject: [Xen-devel] [PATCH 3/3] AMD/IOMMU: replace a few literal numbers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Introduce IOMMU_PDE_NEXT_LEVEL_{MIN,MAX} to replace literal 1, 6, and 7 instances. While doing so replace two uses of memset() by initializers. Signed-off-by: Jan Beulich --- TBD: We should really honor the hats field of union amd_iommu_ext_features, but the specification (or at least the parts I did look at in the course of putting together this patch) is unclear about the maximum valid value in case EFRSup is clear. --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -187,7 +187,8 @@ static int iommu_pde_from_dfn(struct dom table = hd->arch.root_table; level = hd->arch.paging_mode; - BUG_ON( table == NULL || level < 1 || level > 6 ); + BUG_ON(!table || level < IOMMU_PDE_NEXT_LEVEL_MIN || + level > IOMMU_PDE_NEXT_LEVEL_MAX); /* * A frame number past what the current page tables can represent can't @@ -198,7 +199,7 @@ static int iommu_pde_from_dfn(struct dom next_table_mfn = mfn_x(page_to_mfn(table)); - while ( level > 1 ) + while ( level > IOMMU_PDE_NEXT_LEVEL_MIN ) { unsigned int next_level = level - 1; pt_mfn[level] = next_table_mfn; @@ -274,7 +275,7 @@ static int iommu_pde_from_dfn(struct dom level--; } - /* mfn of level 1 page table */ + /* mfn of IOMMU_PDE_NEXT_LEVEL_MIN page table */ pt_mfn[level] = next_table_mfn; return 0; } @@ -284,9 +285,7 @@ int amd_iommu_map_page(struct domain *d, { struct domain_iommu *hd = dom_iommu(d); int rc; - unsigned long pt_mfn[7]; - - memset(pt_mfn, 0, sizeof(pt_mfn)); + unsigned long pt_mfn[IOMMU_PDE_NEXT_LEVEL_MAX + 1] = {}; spin_lock(&hd->arch.mapping_lock); @@ -300,7 +299,8 @@ int amd_iommu_map_page(struct domain *d, return rc; } - if ( iommu_pde_from_dfn(d, dfn_x(dfn), pt_mfn, true) || (pt_mfn[1] == 0) ) + if ( iommu_pde_from_dfn(d, dfn_x(dfn), pt_mfn, true) || + !pt_mfn[IOMMU_PDE_NEXT_LEVEL_MIN] ) { spin_unlock(&hd->arch.mapping_lock); AMD_IOMMU_DEBUG("Invalid IO pagetable entry dfn = %"PRI_dfn"\n", @@ -310,9 +310,11 @@ int amd_iommu_map_page(struct domain *d, } /* Install 4k mapping */ - *flush_flags |= set_iommu_pte_present(pt_mfn[1], dfn_x(dfn), mfn_x(mfn), - 1, (flags & IOMMUF_writable), - (flags & IOMMUF_readable)); + *flush_flags |= set_iommu_pte_present(pt_mfn[IOMMU_PDE_NEXT_LEVEL_MIN], + dfn_x(dfn), mfn_x(mfn), + IOMMU_PDE_NEXT_LEVEL_MIN, + flags & IOMMUF_writable, + flags & IOMMUF_readable); spin_unlock(&hd->arch.mapping_lock); @@ -322,11 +324,9 @@ int amd_iommu_map_page(struct domain *d, int amd_iommu_unmap_page(struct domain *d, dfn_t dfn, unsigned int *flush_flags) { - unsigned long pt_mfn[7]; + unsigned long pt_mfn[IOMMU_PDE_NEXT_LEVEL_MAX + 1] = {}; struct domain_iommu *hd = dom_iommu(d); - memset(pt_mfn, 0, sizeof(pt_mfn)); - spin_lock(&hd->arch.mapping_lock); if ( !hd->arch.root_table ) @@ -344,10 +344,12 @@ int amd_iommu_unmap_page(struct domain * return -EFAULT; } - if ( pt_mfn[1] ) + if ( pt_mfn[IOMMU_PDE_NEXT_LEVEL_MIN] ) { /* Mark PTE as 'page not present'. */ - *flush_flags |= clear_iommu_pte_present(pt_mfn[1], dfn_x(dfn)); + *flush_flags |= + clear_iommu_pte_present(pt_mfn[IOMMU_PDE_NEXT_LEVEL_MIN], + dfn_x(dfn)); } spin_unlock(&hd->arch.mapping_lock); --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -233,14 +233,14 @@ static int __must_check allocate_domain_ int amd_iommu_get_paging_mode(unsigned long entries) { - int level = 1; + int level = IOMMU_PDE_NEXT_LEVEL_MIN; BUG_ON( !entries ); while ( entries > PTE_PER_TABLE_SIZE ) { entries = PTE_PER_TABLE_ALIGN(entries) >> PTE_PER_TABLE_SHIFT; - if ( ++level > 6 ) + if ( ++level > IOMMU_PDE_NEXT_LEVEL_MAX ) return -ENOMEM; } --- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h +++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h @@ -465,6 +465,9 @@ union amd_iommu_x2apic_control { #define IOMMU_PAGE_TABLE_U32_PER_ENTRY (IOMMU_PAGE_TABLE_ENTRY_SIZE / 4) #define IOMMU_PAGE_TABLE_ALIGNMENT 4096 +#define IOMMU_PDE_NEXT_LEVEL_MIN 1 +#define IOMMU_PDE_NEXT_LEVEL_MAX 6 + struct amd_iommu_pte { uint64_t pr:1; uint64_t ignored0:4;