@@ -1335,6 +1335,7 @@ static const struct vex {
{ { 0x45 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsrlv{d,q} */
{ { 0x46 }, 2, T, R, pfx_66, W0, Ln }, /* vpsravd */
{ { 0x47 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsllv{d,q} */
+ { { 0x49, 0xc0 }, 2, F, N, pfx_no, W0, L0 }, /* tilerelease */
{ { 0x50 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusd */
{ { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusds */
{ { 0x52 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwssd */
@@ -247,6 +247,10 @@ int emul_test_get_fpu(
break;
default:
return X86EMUL_UNHANDLEABLE;
+
+ case X86EMUL_FPU_tilecfg:
+ case X86EMUL_FPU_tile:
+ return cpu_has_amx_tile ? X86EMUL_OKAY : X86EMUL_UNHANDLEABLE;
}
return X86EMUL_OKAY;
}
@@ -475,6 +475,7 @@ static const struct ext0f38_table {
[0x43] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq },
[0x44] = { .simd_size = simd_packed_int, .two_op = 1, .d8s = d8s_vl },
[0x45 ... 0x47] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
+ [0x49] = { .simd_size = simd_other, .two_op = 1 },
[0x4c] = { .simd_size = simd_packed_fp, .two_op = 1, .d8s = d8s_vl },
[0x4d] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq },
[0x4e] = { .simd_size = simd_packed_fp, .two_op = 1, .d8s = d8s_vl },
@@ -2046,6 +2047,7 @@ amd_like(const struct x86_emulate_ctxt *
#define vcpu_has_avx512_4fmaps() (ctxt->cpuid->feat.avx512_4fmaps)
#define vcpu_has_avx512_vp2intersect() (ctxt->cpuid->feat.avx512_vp2intersect)
#define vcpu_has_serialize() (ctxt->cpuid->feat.serialize)
+#define vcpu_has_amx_tile() (ctxt->cpuid->feat.amx_tile)
#define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni)
#define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16)
@@ -9500,6 +9502,24 @@ x86_emulate(
generate_exception_if(vex.l, EXC_UD);
goto simd_0f_avx;
+ case X86EMUL_OPC_VEX(0x0f38, 0x49):
+ generate_exception_if(!mode_64bit() || vex.l || vex.w, EXC_UD);
+ if ( ea.type == OP_REG )
+ {
+ switch ( modrm )
+ {
+ case 0xc0: /* tilerelease */
+ host_and_vcpu_must_have(amx_tile);
+ get_fpu(X86EMUL_FPU_tilecfg);
+ op_bytes = 1; /* fake */
+ goto simd_0f_common;
+
+ default:
+ goto unrecognized_insn;
+ }
+ }
+ goto unimplemented_insn;
+
case X86EMUL_OPC_VEX_66(0x0f38, 0x50): /* vpdpbusd [xy]mm/mem,[xy]mm,[xy]mm */
case X86EMUL_OPC_VEX_66(0x0f38, 0x51): /* vpdpbusds [xy]mm/mem,[xy]mm,[xy]mm */
case X86EMUL_OPC_VEX_66(0x0f38, 0x52): /* vpdpwssd [xy]mm/mem,[xy]mm,[xy]mm */
@@ -133,6 +133,7 @@
#define cpu_has_avx512_vp2intersect boot_cpu_has(X86_FEATURE_AVX512_VP2INTERSECT)
#define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)
#define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE)
+#define cpu_has_amx_tile boot_cpu_has(X86_FEATURE_AMX_TILE)
/* CPUID level 0x00000007:1.eax */
#define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI)
This is relatively straightforward, and hence best suited to introduce a few other general pieces. Testing of this will be added once a sensible test can be put together, i.e. when support for other insns is also there. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- v2: New.