| Message ID | 0ebb0de3-2500-a9a2-8128-64b9d4a27cb7@suse.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/mwait-idle: updates from Linux | expand |
On Mon, Sep 06, 2021 at 02:59:46PM +0200, Jan Beulich wrote: > From: Alexander Monakov <amonakov@ispras.ru> > > Intel SDM does not explicitly say that entering a C-state via MWAIT will > implicitly flush CPU caches as appropriate for that C-state. However, > documentation for individual Intel CPU generations does mention this > behavior. > > Since intel_idle binds to any Intel CPU with MWAIT, list this assumption > of MWAIT behavior. > > In passing, reword opening comment to make it clear that the driver can > load on any old and future Intel CPU with MWAIT. > > Signed-off-by: Alexander Monakov <amonakov@ispras.ru> > Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> > [Linux commit: 8bb2e2a887afdf8a39e68fa0dccf82a168aae655] > > Dropped "reword opending comment" part - this doesn't apply to our code: > First thing mwait_idle_probe() does is call x86_match_cpu(); we do not > have a 2nd such call looking for just MWAIT (in order to the use _CST > data directly, which we can't get our hands at _CST at this point yet). > > Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Roger Pau Monné <roger.pau@citrix.com> Thanks, Roger.
--- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -31,6 +31,10 @@ * * Chipset BM_STS (bus master status) bit is a NOP * for preventing entry into deep C-states + * + * CPU will flush caches as needed when entering a C-state via MWAIT + * (in contrast to entering ACPI C3, in which case the WBINVD + * instruction needs to be executed to flush the caches) */ /*