From patchwork Thu Dec 17 17:29:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 7875471 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EB3D6BEEE5 for ; Thu, 17 Dec 2015 17:33:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E12D20444 for ; Thu, 17 Dec 2015 17:33:17 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C175120412 for ; Thu, 17 Dec 2015 17:33:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1a9cOI-0000cT-1T; Thu, 17 Dec 2015 17:30:58 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1a9cOF-0000cD-OZ for xen-devel@lists.xenproject.org; Thu, 17 Dec 2015 17:30:55 +0000 Received: from [85.158.143.35] by server-1.bemta-4.messagelabs.com id 68/2C-21571-F41F2765; Thu, 17 Dec 2015 17:30:55 +0000 X-Env-Sender: prvs=78612b3c6=julien.grall@citrix.com X-Msg-Ref: server-8.tower-21.messagelabs.com!1450373452!5938278!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 12812 invoked from network); 17 Dec 2015 17:30:54 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-8.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 17 Dec 2015 17:30:54 -0000 X-IronPort-AV: E=Sophos;i="5.20,442,1444694400"; d="scan'208";a="326052119" From: Julien Grall To: Date: Thu, 17 Dec 2015 17:29:10 +0000 Message-ID: <1450373350-9085-1-git-send-email-julien.grall@citrix.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 X-DLP: MIA2 Cc: Julien Grall , ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH] xen/arm: vgic: Clarify some comments after 5d495f4 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Ian pointed out that the definition of "offset" and "appropriate boundary" in the comments added by "xen/arm: vgic: Optimize the way to store the target vCPU in the rank" were not cleared. Clarify them by explicitly mentionning the offset is in byte and the appropriate boundary is ITARGET/IROUTER Signed-off-by: Julien Grall --- xen/arch/arm/vgic-v2.c | 4 ++-- xen/arch/arm/vgic-v3.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 07316e8..032b964 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -65,7 +65,7 @@ void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, * Fetch an ITARGETSR register based on the offset from ITARGETSR0. Only * one vCPU will be listed for a given vIRQ. * - * Note the offset will be aligned to the appropriate boundary. + * Note the byte offset will be aligned to an ITARGETSR boundary. */ static uint32_t vgic_fetch_itargetsr(struct vgic_irq_rank *rank, unsigned int offset) @@ -88,7 +88,7 @@ static uint32_t vgic_fetch_itargetsr(struct vgic_irq_rank *rank, * Store an ITARGETSR register in a convenient way and migrate the vIRQ * if necessary. This function only deals with ITARGETSR8 and onwards. * - * Note the offset will be aligned to the appropriate boundary. + * Note the byte offset will be aligned to an ITARGETSR boundary. */ static void vgic_store_itargetsr(struct domain *d, struct vgic_irq_rank *rank, unsigned int offset, uint32_t itargetsr) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index f01bbd9..6ab8002 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -94,7 +94,7 @@ static struct vcpu *vgic_v3_irouter_to_vcpu(struct domain *d, uint64_t irouter) * Fetch an IROUTER register based on the offset from IROUTER0. Only one * vCPU will be listed for a given vIRQ. * - * Note the offset will be aligned to the appropriate boundary. + * Note the byte offset will be aligned to an IROUTER boundary. */ static uint64_t vgic_fetch_irouter(struct vgic_irq_rank *rank, unsigned int offset)